The Triton II (Official name 82430HX) was a version of Intel's Triton processor chip set with all the features of the Triton I plus support for ECC, parity RAM, two-way SMP, USB, and Concurrent PCI to improve speed.
It consists of one 82439HX TXC and one 82371SB PIIX3.
References
This article was originally based on material from the Free On_line Dictionary of Computing, which is licensed under the GFDL.
In addition to the traditional features, this chip set supports: EDO DRAM to increase the bandwidth of the DRAM interface; "pipelined burst SRAM" for a cheaper, faster second level cache; "bus master IDE" control logic to reduce processor load; a plug and play port for easy implementation of functions such as audio.
The Triton I chipset (official name 82430FX) consists of 4 chips: one 82437FX TSC (Triton Sysetm Controller), two 82438FX TDP (Triton Data Path), and one 82371FB PIIX (PCI IDE Xcellerator).
It supports PB Cache, EDO DRAM, and a maximum PCI and memory burst data transfer rate of 100 megabytes per second.
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