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Introduction
ATPG, or Automatic test pattern generation is an electronic design automation tool that attempts to find an input (or test) sequence that, when applied to a digital circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. The effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. ATPG efficiency is another important consideration. It is influenced by the fault model under consideration, the type of circuit under test (full scan, synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transistor, switch), and the required test quality. Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. ...
Digital circuits are electric circuits based on a number of discrete voltage levels. ...
Basic fault models in digital circuits include: the stuck-at fault model the crosspoint fault model Categories: Stub | Digital electronics | Electronic design ...
Basics of ATPG A fault model is a hypothesis of how the circuit may go wrong in the manufacturing process. A fault is said to be detected by a test pattern if, when applying the pattern to the circuit, different logic values can be observed, in at least one of the circuit's primary outputs, between the original circuit and the faulty circuit. ATPG for a given target fault consists of two phases: Fault activation and Fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault. Fault propagation propagates the fault effect forward by sensitizing a path from the fault site to a primary output.
The Stuck-at fault model In the past several decades, the most popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent and transient faults that can appear randomly through time. The fault model is structural because it is defined based on a structural gate-level circuit model.
A pattern set with 100% stuck-at fault coverage consists of tests to detect every possible stuck-at fault in a circuit. 100% stuck-at fault coverage does not necessarily guarantee high quality, since faults of many other kinds (such as bridging faults or opens) often occur.
Sequential ATPG Sequential-circuit ATPG searches for a sequence of vectors to detect a particular fault through the space of all possible vector sequences. Various search strategies and heuristics have been devised to find a shorter sequence and/or to find a sequence faster. However, according to reported results, no single strategy/heuristic out-performs others for all applications/circuits. This observation implies that a test generator should include a comprehensive set of heuristics.
Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational circuit. These factors make the complexity of sequential ATPG much higher than that of combinational ATPG.
Due to the high complexity of the sequential ATPG, it remains a challenging task for large, highly sequential circuits that do not incorporate any design for testability (DfT) scheme. However, these test generators, combined with low-overhead DfT techniques such as partial scan, have shown a certain degree of success in testing large designs. For designs that are sensitive to area and/or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.
ATPG and nanometer technologies Historically, ATPG has focused on a set of faults derived from a gate-level fault model. As design trends move toward nanometer te chnology, new ATPG problems are emerging. During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance. Current modeling and vector-generation techniques must give way to new techniques that consider timing information during test generation, that are scalable to larger designs, and that can capture extreme design conditions. For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed.
Algorithmic Methods Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity. Therefore many different ATPG methods have been developed to address combinatorial and sequential circuits. Very-large-scale integration (VLSI) of systems of transistor-based circuits into integrated circuits on a single chip first occurred in the 1980s as part of the semiconductor and communication technologies that were being developed. ...
This article is not about combinatory logic, a topic in mathematical logic. ...
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present input but also on the history of the input. ...
- Early test generation algorithms such as boolean difference and literal proposition were not practical to implement on a computer.
- The D Algorithm was the first practical test generation algorithm in terms of memory requirements. The D Algorithm introduced D Notation which continues to be used in most ATPG algorithms.
- Path Oriented Decision Making (PODEM) is an improvement over the D Algorithm. PODEM was created in 1981 when shortcomings in D Algorithm became evident when design innovations resulted in circuits that D Algorithm could not realize.
- Fan-Out Oriented (FAN) is an improvement over PODEM. It limits the ATPG search space to reduce computation time and accelerates backtracing.
- Methods based on Satisfiability are sometimes used to generate test vectors.
- Pseudorandom test generation is the simplest method of creating tests. It uses a pseudorandom number generator to generate test vectors.
Flowcharts are often used to represent algorithms. ...
The Boolean satisfiability problem (SAT) is a decision problem considered in complexity theory. ...
A pseudo-random number is a number belonging to a sequence which appears to be random, but can in fact be generated by a finite computation. ...
See also Design-for-Test Design for Test (also known as Design for Testability, or DFT for short) is a methodology commonly employed during the design of integrated circuits. ...
Basic fault models in digital circuits include: the stuck-at fault model the crosspoint fault model Categories: Stub | Digital electronics | Electronic design ...
The acronym ASIC, depending on context, may stand for: Application-specific integrated circuit ASIC programming language Australian Securities and Investments Commission This is a disambiguation page — a navigational aid which lists pages that might otherwise share the same title. ...
A VHSIC is a Very-High-Speed Integrated Circuit, a type of digital logic circuit. ...
References - Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0849330963 A survey of the field, from which the above summary was derived, with permission.
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