In computer architecture, a branch delay instruction is an instruction immediately following a conditional branch instruction which is executed whether or not the branch is taken. The location of such an instruction in the pipeline is called a branch delay slot. Branch delay slots are found not only in several RISC architectures including MIPS, PA-RISC and SPARC but also in DSP architectures including µPD77230 and TMS320C3x. In computer engineering, computer architecture is the conceptual design and fundamental operational structure of a computer system. ... A conditional branch is a basic logical structure. ... In computer science, an instruction typically refers to a single operation of a processor within a computer architecture. ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... A MIPS R4400 microprocessor made by Toshiba MIPS, for Microprocessor without interlocked pipeline stages, is a RISC microprocessor architecture developed by MIPS Computer Systems Inc. ... PA-RISC is a microprocessor architecture developed by Hewlett-Packards Systems & VLSI Technology Operation. ... Sun UltraSPARC II Microprocessor Sun UltraSPARC T1 (Niagara 8 Core) SPARC (Scalable Processor ARChitecture) is a pure big-endian RISC microprocessor architecture originally designed in 1985 by Sun Microsystems. ... A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real-time. ... Texas Instruments TMS320 is a blanket name for a series of digital signal processors from Texas Instruments. ...

The goal of a pipelined architecture is to keep the pipeline full of instructions at all times. The branch delay slot is a side-effect of pipelined architectures due to the branch hazard, i.e. the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter. Each cycle where a stall is inserted is considered one branch delay slot. A more sophisticated design would execute program instructions which are not dependent on the result of the branch instruction. This optimization can be performed in software at compile time by moving instructions into branch delay slots in the in-memory instruction stream, if the hardware supports this. Another side-effect is that special handling should be taken care of managing breakpoint on instructions as well as stepping while debugging within branch delay slot. This article needs to be cleaned up to conform to a higher standard of quality. ... In computer architecture, a hazard is a potential problem that can happen in a pipelined processor. ... A stall is the slowing or stopping of a process. ... The program counter (also called the instruction pointer in some computers) is a register in a computer processor which indicates where the computer is in its instruction sequence. ... Computer software (or simply software) refers to one or more computer programs and data held in the storage of a computer for some purpose. ... In computer science, compile time, as opposed to runtime, is the time when a compiler compiles code written in a programming language into an executable form. ... A breakpoint, in software development, is an intentional stopping or pausing place in a program, put in place for debugging purposes. ... Debugging is a methodical process of finding and reducing the number of bugs, or defects, in a computer program or a piece of electronic hardware thus making it behave as expected. ...

The number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of register forwarding, what stage of the pipeline the branch conditions are computed, whether or not a branch target buffer (BTB) is used and many other factors. In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ...

By using branch prediction techniques and speculative execution, many of these branch delay slots are efficiently utilitized, reducing the performance penalty incurred by these branch instructions. In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ... In computer science, speculative execution is the execution of code whose result may not actually be needed. ...

External links

• Branch Prediction Schemes