Static CMOS Inverter

Complementary metal–oxide–semiconductor (CMOS) (pronounced "see-moss", IPA: /siːmɔːs, ˈsiːmɒs/), is a major class of integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. CMOS refers to: The complementary metal–oxide–semiconductor class of integrated circuits Nonvolatile BIOS memory in a personal computer (often called CMOS for historical reasons) An active pixel sensor or CMOS sensor in a digital camera In writing, The Chicago Manual of Style Canadian Meteorological and Oceanographic Society The NASDAQ... Image File history File links This is a lossless scalable vector image. ... Image File history File links This is a lossless scalable vector image. ... Integrated circuit of Atmel Diopsis 740 System on Chip showing memory blocks, logic and input/output pads around the periphery Microchips with a transparent window, showing the integrated circuit inside. ... A microprocessor is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). ... It has been suggested that this article or section be merged with embedded microprocessor. ... Static random access memory (SRAM) is a type of semiconductor memory. ... Digital circuits are electric circuits based on a number of discrete voltage levels. ... A dismantled USB webcam, with and without a lens over its (Bayer format) image sensor. ... In the field of electronic circuit design, data converters are components that convert information from analog domain to the digital domain or vice versa. ... A transceiver is a device that has both a transmitter and a receiver which are combined in to one. ...

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. A P-type semiconductor is obtained by carrying out a process of doping, that is adding a certain type of atoms to the semiconductor in order to increase the number of free (in this case positive) charges. ... An N-type semiconductor is obtained by carrying out a process of doping, that is adding a certain type of atoms to the semiconductor in order to increase the number of free (in this case negative) charge carriers. ... The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is by far the most common field-effect transistor in both digital and analog circuits. ...

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL). CMOS also allows a high density of logic functions on a chip. Associated with all electronic circuits is noise. ... In electrical engineering, power consumption refers to the electrical energy over time that must be supplied to an electrical device to maintain its operation. ... Assorted discrete transistors A transistor is a semiconductor device, commonly used as an amplifier or an electrically controlled switch. ... Waste heat is the by-product heat of machines and technical processes for which no useful application is found. ... A Motorola 68000-based computer with various TTL chips. ...

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Instead of metal, current gate electrodes (including those up to the 65 nanometer technology node) are almost always made from a different material, polysilicon, but the terms MOS and CMOS nevertheless continue to be used for the modern descendants of the original process. Metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and beyond ^[1]. Large power N-channel field effect transistor The field-effect transistor (FET) is a type of transistor that relies on an electric field to control the shape and hence the conductivity of a channel in a semiconductor material. ... A semiconductor is a solid whose electrical conductivity is in between that of a conductor and that of an insulator, and can be controlled over a wide range, either permanently or dynamically. ... The 65 nanometer (65 nm) process is (as of 2006) the most advanced lithographic node for volume semiconductor manufacturing, however it will soon be eclipsed when 45 nanometer lithography becomes commercially viable. ... Polycrystalline silicon or polysilicon or poly-Si is a material consisting of multiple small silicon crystals, and has long been used as the conducting gate material in MOSFET and CMOS processing technologies. ... A metal gate, in the context of a lateral Metal-Oxide-Semiconductor MOS stack, is just that--the gate material is made from a metal. ... High K dielectric may be used in next generation electronic component to replace SiO2 Gate dielectric. ... The 45 nanometer (45 nm) process is the next milestone (to be commercially viable in mid 2007 to early 2008) in CMOS fabrication. ...

Technical details

"CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power and is more dense than other implementations having the same functionality. As this advantage has grown and become more important, CMOS processes and variants have come to dominate, so that the vast majority of modern integrated circuit manufacturing is on CMOS processes ^{[citation needed]}. In electronics, the term low-power means one of two things about a device: Said of a radio transmitter, that the power of the broadcast is less, i. ...

Structure

CMOS logic uses a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (for instance, in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions (or hundreds of millions) of transistors of both types on a rectangular piece of silicon of between 0.1 and 4 square centimeters ^{[citation needed]}. These devices are commonly called "chips", although within the industry they are also referred to as "die" (singular) or "dice" (plural). The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is by far the most common field-effect transistor in both digital and analog circuits. ... A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. ... Digital circuits are electric circuits based on a number of discrete voltage levels. ... This article is about the machine. ... Copy of the original phone of Alexander Graham Bell at the Musée des Arts et Métiers in Paris Telecommunication is the assisted transmission of signals over a distance for the purpose of communication. ... Signal processing is the processing, amplification and interpretation of signals, and deals with the analysis and manipulation of signals. ...

In CMOS logic, a collection of n-type MOSFETs are arranged in a pull-down network between the output node and the lower-voltage power supply rail, named V_ss, which often has ground potential. Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the output and the higher-voltage rail, named V_dd. Pull-up and pull-down refer to the idea that the output node, which exhibits some internal capacitance, is charged or discharged by the connected pull-up and pull-down networks. By asserting or de-asserting the inputs to the CMOS circuit, individual transistors along the pull-up and pull-down networks become conductive, and a path is connected from the output node to one of the voltage rails. A digital CMOS circuit cannot be in a pull-up and pull-down state at the same time, except when switching between the two states. Each input is connected to both the pull-up and pull-down networks in a complementary fashion, so that when an n-type transistor on the pull-down path is off, the p-type on the pull-up path is on, and vice-versa. A pull-up resistor is used in the design of electronic logic circuits. ... This article does not cite any references or sources. ... In electrical engineering, the term node refers to any point on a circuit where the voltage is the same. ... It has been suggested that this article or section be merged with Current source. ... VSS may refer to: VSS Valley Security Services, a UK based provider of security and fire safety solutions. ... It has been suggested that Ground conductor be merged into this article or section. ... nMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. ... A pull-up resistor is used in the design of electronic logic circuits. ... Almost all integrated circuits (ICs) have at least two pins which connect to the power rails of the circuit they are installed in. ... Capacitance is a measure of the amount of electric charge stored (or separated) for a given electric potential. ... En [ [ ciencia ] ] y [ [ ingeniería ] ], los conductores son los materiales de los cuales contenga las cargas movibles [ [ electricidad ] ]. Cuando una diferencia potencial eléctrica se impresiona a través de puntos separados en un conductor, las cargas móviles dentro del conductor se fuerzan para moverse, y una corriente el... Electrical switches. ...

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching (dynamic power). On a typical ASIC in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happen once every ten nanoseconds. NMOS logic dissipates power whenever the output is low (static power), because there is a current path from V_dd to V_ss through the load resistor and the n-type network. This article does not cite any references or sources. ...

P-type MOSFETs are complementary to n-type because they turn on when their gate voltage goes sufficiently below their source voltage, and because they can pull the drain all the way to V_dd. Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is off, and vice-versa.

Example: NAND gate

NAND gate in CMOS logic

As an example, shown on the right is a circuit diagram of a NAND gate in CMOS logic. Image File history File links CMOS_NAND.svg‎ File historyClick on a date/time to view the file as it appeared at that time. ... Image File history File links CMOS_NAND.svg‎ File historyClick on a date/time to view the file as it appeared at that time. ... ... The circuit diagram for a 4 bit TTL counter, a type of state machine A circuit diagram (also known as an electrical diagram, elementary diagram, or electronic schematic) is a simplified conventional pictorial representation of an electrical circuit. ... ...

If both of the A and B inputs are high, then both the n-type transistors (bottom half of the diagram) will conduct, neither of the p-type transistors (top half) will conduct, and a conductive path will be established between the output and V_ss, bringing the output low. If either of the A or B inputs is low, one of the n-type transistors will not conduct, one of the p-type transistors will, and a conductive path will be established between the output and V_dd, bringing the output high.

Another advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise. International safety symbol Caution, risk of electric shock (ISO 3864), colloquially known as high voltage symbol. ...

See Logical effort for a method of calculating delay in a CMOS circuit. The method of logical effort, a term coined by Ivan Sutherland and Robert Sproull in 1991, is a straight-forward technique used to estimate delay in a CMOS circuit. ...

Example: NAND gate in physical layout

The physical layout of a NAND circuit (based on the CMOS logic example given)

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection. Image File history File links This is a lossless scalable vector image. ... Image File history File links This is a lossless scalable vector image. ... Integrated circuit layout, also known IC layout or IC mask layout is the representation of an integrated circuit in terms of planar geometric shapes that correspond to shapes actually drawn on photomasks used in semiconductor device fabrication. ... ... Polycrystalline silicon or polysilicon or poly-Si is a material consisting of multiple small silicon crystals, and has long been used as the conducting gate material in MOSFET and CMOS processing technologies. ...

The inputs to the NAND (illustrated in green coloring) are in polysilicon. The CMOS transistors (devices) are formed by the intersection of the polysilicon and diffusion: N diffusion for the N device; P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares. The physical layout example matches the NAND logic circuit given in the previous example. ... Polycrystalline silicon or polysilicon or poly-Si is a material consisting of multiple small silicon crystals, and has long been used as the conducting gate material in MOSFET and CMOS processing technologies. ... Polycrystalline silicon or polysilicon or poly-Si is a material consisting of multiple small silicon crystals, and has long been used as the conducting gate material in MOSFET and CMOS processing technologies. ... Polycrystalline silicon or polysilicon or poly-Si is a material consisting of multiple small silicon crystals, and has long been used as the conducting gate material in MOSFET and CMOS processing technologies. ... Integrated circuit layout, also known IC layout or IC mask layout is the representation of an integrated circuit in terms of planar geometric shapes that correspond to shapes actually drawn on photomasks used in semiconductor device fabrication. ... ...

The N device is manufactured on a P-type substrate. The P devices is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to V_SS and an N-type n-well tap is connected to V_DD to prevent latchup. A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure, which then acts as a short circuit, disrupting proper functioning of the part and possibly even leading to its destruction due to overcurrent. ...

Power: switching and leakage

CMOS circuits dissipate power by charging and discharging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV²f.

A different form of power consumption became noticeable in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. During the middle of these transitions, both the NMOS and PMOS networks are partially conductive, and current flows directly from V_dd to V_ss. The power thus used is called crowbar power. Careful design which avoids weakly driven long skinny wires has ameliorated this effect, and crowbar power is nearly always substantially smaller than switching power. For the band, see 1990s (band). ... See MOSFET ...

Both NMOS and PMOS transistors have a threshold gate-to-source voltage, below which the current through the device drops exponentially. Historically, CMOS designs operated at supply voltages much larger than their threshold voltages (V_dd might have been 5 V, and V_th for both NMOS and PMOS might have been 700 mV). But as supply voltages have come down to conserve power the V_dd to V_ss short circuit is avoided. Depletion Region of an NMOS The threshold voltage of a MOSFET is usually defined as the gate voltage where a depletion region forms in the substrate (body) of the transistor. ...

However, to speed up the designs, manufacturers have switched to gate materials which lead to lower voltage thresholds and a modern NMOS transistor with a V_th of 200 mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which try to optimize their fabrication processes for minimum power dissipation during operation have been lowering V_th so that leakage power begins to approximate switching power. As a result, these devices dissipate considerable power even when not switching. Leakage power reduction using new material and system design is critical to sustaining scaling of CMOS. The industry is contemplating the introduction of High-k Dielectrics to combat the increasing gate leakage current by replacing the silicon dioxide that are the conventional gate dielectrics with materials having a higher dielectric constant. A good overview of leakage and reduction methods are explained in Leakage in Nanometer CMOS Technologies ISBN 0-387-25737-3. Subthreshold leakage of an NMOS Subthreshold leakage is the current that flows from the drain to source of a MOSFET when the transistor is supposed to be off. ... The term high-κ dielectric refers to materials with a high dielectric constant (κ) (relative to silicon dioxide) which are going to be used [1] in next generation semiconductor components to replace the SiO2 gate dielectric, especially for the low standby power (LSTP) applications at the 45 nm technology node. ... R-phrases R42 R43 R49 S-phrases S22 S36 S37 S45 S53 Flash point non-flammable Supplementary data page Structure and properties n, εr, etc. ... The relative dielectric constant of a material under given conditions is a measure of the extent to which it concentrates electrostatic lines of flux. ...

See also

• Magic is open-source software often used as a layout tool for CMOS circuits.
• The combination of MEMS sensors with digital signal processors on one single CMOS chip is sometimes known an CMOSens.

Magic is a Very-large-scale integration layout tool originally written by John Ousterhout at UC Berkeley during the 1980s. ... A mite next to a gear set produced using MEMS. Courtesy Sandia National Laboratories, SUMMiTTM Technologies, www. ... A sensor is a technological device or biological organ that detects, or senses, a signal or physical condition. ...

References

External links

• CMOS gate description and interactive illustrations
• LASI is a "general purpose" IC layout CAD tool. It is a free download and can be used as a layout tool for CMOS circuits.