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Cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence. Memory coherence (also cache coherence or cache consistency) is the property of the shared memory systems (multiprocessors and distributed shared memory systems) in which any shared piece of memory (cache line or memory page) gives consistent values with accordance to earlier agreed consistency model despite accesses (maybe parallel) from different...
 Multiple Caches of Common Resource When clients in a system, particularly CPUs in a multiprocessing system, maintain caches of a common memory resource, problems arise. Referring to the figure, if the top client has a copy of a memory block from a previous read and the bottom client changes that memory block, the top client could be left with an invalid cache of memory without it knowing any better. Cache coherence is intended to manage such conflicts and maintain consistency between cache and memory. Image File history File links File links The following pages link to this file: Cache coherency ...
Image File history File links File links The following pages link to this file: Cache coherency ...
Multiprocessing is traditionally known as the use of multiple concurrent processes in a system as opposed to a single process at any one instant. ...
Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ...
Cache Coherence Mechanisms
Directory-based cache coherence mechanisms maintain a central directory of cached blocks. Directory-based coherence protocols are a set of cache coherence protocols, that is, protocols which ensure cache coherence or memory coherence between multiple nodes of multiprocessor or distributed shared memory systems, such as ccNUMA. In such protocols, directories track where each page, or block of memory, has been cached. ...
Snooping is the process where the individual caches monitor address lines for accesses to memory locations that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location. Bus sniffing or Bus snooping is a technique used in distributed shared memory systems and multiprocessors aimed at achieving cache coherence. ...
Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory.
Distributed shared memory systems mimic these mechanisms in an attempt to maintain consistency between blocks of memory in loosely coupled systems. Distributed Shared Memory (DSM), in computer science, refers to a wide class of software and hardware implementations, in which each node of a cluster has access to a large shared memory in addition to each nodes limited non-shared private memory. ...
Coherence Models Various models and protocols have been devised for maintaining cache coherence, such as the MSI protocol, MESI protocol, MOSI protocol and the MOESI protocol. Choice of consistency model is crucial to designing a cache coherent system. Coherence models differ in performance and scalability so each must be evaluated for every system design. This protocol consists of 3 states: Modified: The block has been modified by the processor that owns this cache. ...
The MESI protocol (known also as Illinois protocol) is a widely used cache coherency and memory coherence protocol, which was later introduced by Intel in the Pentium processor to support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor...
This is an extention of the basic MSI cache coherency protocol. ...
This is a full cache coherency protocol that encompasses all of the possible states commonly used in other protocols. ...
In computer science, in a distributed system such as a distributed shared memory system or a distributed data store such as a database, filesystem, or web caching system, there are a number of possible data consistency models. ...
Further more, transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.
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