Layout of the IBM Cell die

Cell is a microprocessor architecture jointly developed by a Sony, Toshiba, and IBM, an alliance known as "STI." The architectural design and first implementation were carried out at the STI Design Center over a four-year period beginning March 2001 on a budget reported by IBM as approaching US$400 million.^[1] Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part. Cell combines a general-purpose Power Architecture core of modest performance with streamlined coprocessing elements^[2] which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.^[2] Image File history File linksMetadata Cell_Broadband_Engine_Processor. ... Image File history File linksMetadata Cell_Broadband_Engine_Processor. ... A microprocessor is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). ... Sony Corporation ) is a Japanese multinational corporation and one of the worlds largest media conglomerates with revenue of $68. ... Toshiba Corporations headquarters (Center) in Hamamatsucho, Tokyo Toshiba Corporation sales by division for year ending March, 31 2005 Toshiba Corporation ) (TYO: 6502 ) is a multinational high technology electrical and electronics manufacturing firm, headquartered in Tokyo, Japan. ... International Business Machines Corporation (known as IBM or Big Blue; NYSE: IBM) is a multinational computer technology and consulting corporation headquartered in Armonk, New York, USA. The company is one of the few information technology companies with a continuous history dating back to the 19th century. ... ISO 4217 Code USD User(s) the United States, the British Indian Ocean Territory,[1] the British Virgin Islands, Cambodia, East Timor, Ecuador, El Salvador, the Marshall Islands, Micronesia, Palau, Panama, Turks and Caicos Islands, and the insular areas of the United States Inflation 2. ... The Power Architecture logo Power Architecture is a broad term to describe similar instruction sets for RISC microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi. ... This article or section does not adequately cite its references or sources. ... This article or section does not cite its references or sources. ... ... A vector processor, or array processor, is a CPU design that is able to run mathematical operations on a large number of data elements very quickly. ...

The first major commercial application of Cell was in Sony's PlayStation 3 game console. Mercury Computer Systems has a dual Cell server, a dual Cell blade configuration, a rugged computer, and a PCI Express accelerator board available in different stages of production. Toshiba has announced plans to incorporate Cell in high definition television sets. Exotic features such as the XDR memory subsystem and coherent Element Interconnect Bus (EIB) interconnect^[3] appear to position Cell for future applications in the supercomputing space to exploit the Cell processor's prowess in floating point kernels. IBM has announced plans to incorporate Cell processors as add-on cards into IBM System z9 mainframes, to enable them to be used as servers for MMORPGs^[4] PlayStation 3 , trademarked PLAYSTATION®3,[7] commonly abbreviated PS3) is Sony Computer Entertainments third video game console. ... Four different video game consoles from different generations. ... Mercury Computer Systems, Inc. ... IBM HS20 blade server. ... Projection screen in a home theater, displaying a high-definition television image. ... XDR DRAM is a high performance RAM Interface like SDR-SDRAM and DDR-SDRAM. The XDR solution was engineered to be effective in small high-bandwidth consumer systems, high-performance main memory applications, and flagship GPUs. ... A supercomputer is a device for turning compute-bound problems into I/O-bound problems. ... A floating-point number is a digital representation for a number in a certain subset of the rational numbers, and is often used to approximate an arbitrary real number on a computer. ... IBM System z9 Enterprise Class IBM System z9 is the newest and most powerful line of IBM mainframes. ... An image from World of Warcraft, one of the largest commercial MMORPGs as of 2004, based on active subscriptions. ...

The Cell architecture includes a novel memory coherence architecture for which IBM received many patents. The architecture emphasizes efficiency/watt, prioritizes bandwidth over latency, and favors peak computational throughput over simplicity of program code. For these reasons, Cell is widely regarded as a challenging environment for software development.^[5] IBM provides a comprehensive Linux-based Cell development platform to assist developers in confronting these challenges.^[6] Software adoption remains a key issue in whether Cell ultimately delivers on its performance potential. Despite those challenges, research has indicated that Cell excels at several types of scientific computation.^[7] Memory coherence (also cache coherence or cache consistency) is the property of the shared memory systems (multiprocessors and distributed shared memory systems) in which any shared piece of memory (cache line or memory page) gives consistent values with accordance to earlier agreed consistency model despite accesses (maybe parallel) from different... A patent is a set of exclusive rights granted by a state to a patentee for a fixed period of time in exchange for a disclosure of an invention. ... This article does not cite any references or sources. ... Lag is a common term used to describe a symptom often encountered in computing and especially networked systems, where results of actions appear much later than expected. ... In information technology, throughput is the rate at which a computer or network sends or receives data. ... In computer programming, the word code refers to instructions to a computer in a programming language. ... Software engineering is the application of a systematic, disciplined, quantifiable approach to the development, operation, and maintenance of software. ... Linux (IPA pronunciation: ) is a Unix-like computer operating system. ...

In November 2006, David A. Bader at Georgia Tech was selected by Sony, Toshiba, and IBM from more than a dozen universities^[8] to direct the first STI Center of Competence for the Cell Processor.^[9][10] This partnership is designed to build a community of programmers and broaden industry support for the Cell processor.^[8][9] There is a Cell Programming tutorial video available.^[11] David A. Bader is an Associate Professor in the College of Computing at Georgia Institute of Technology. ... Georgia Institute of Technology The Georgia Institute of Technology, or Georgia Tech, is located in Atlanta, Georgia, U.S.A. With over 16,000 students, Georgia Tech is one of four public research universities in the University System of Georgia. ... The Sony Toshiba IBM Center of Competence for the Cell Processor is the first Center of Competence dedicated to the promotion and development of Sony Toshiba IBMs Cell microprocessor, an eight-core multiprocessor designed using principles of parallellism and memory latency. ...

History

In 2000, Sony Computer Entertainment, Toshiba Corporation, and IBM formed an alliance ("STI") to design and manufacture the processor. Cell architecture Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. ... Software development for the cell microprocessor involve a mixture of conventional development practices for the POWER architecture-compatible PPU core, and novel software development challenges with regards to the functionally reduced SPU coprocessors. ... // IBM has published information concerning two different versions of Cell in this process, an early engineering sample designated DD1, and an enhanced version designated DD2 intended for production. ... Sony Computer Entertainment, Incorporated ) (SCEI) is a Japanese video game company specializing in a variety of areas in the video game industry, mostly in video game consoles and is a full subsidiary of Sony Corporation that was established on November 16, 1993 in Tokyo, Japan. ... Toshiba Corporations headquarters in Hamamatsucho, Tokyo Toshiba Corporation sales by division for year ending March, 31 2005 Toshiba Corporation (東芝, Tōshiba) TYO: 6502 is a Japanese high technology electrical and electronics manufacturing firm, headquartered in Tokyo, Japan. ... International Business Machines Corporation (known as IBM or Big Blue; NYSE: IBM) is a multinational computer technology and consulting corporation headquartered in Armonk, New York, USA. The company is one of the few information technology companies with a continuous history dating back to the 19th century. ...

The STI Design Center in Austin, Texas opened in March 2001.^[12] The Cell was designed over a period of four years, using enhanced versions of the design tools for the POWER4 processor. Over 400 engineers from the three companies worked together in Austin, with critical support from eleven of IBM's design centers.^[12] Nickname: Location in the state of Texas Coordinates: , Country United States State Texas Counties Travis County, Williamson County Government  - Mayor Will Wynn Area  - City  296. ... To meet Wikipedias quality standards, this article or section may require cleanup. ...

During this period, IBM filed many patents pertaining to the Cell architecture, manufacturing process, and software environment. An early patent version of the Broadband Engine was shown to be a chip package comprising four "Processing Elements," which was the patent's description for what is now known as the "Power Processing Element." Each Processing Element contained 8 "APUs," which are now referred to as SPEs on the current Broadband Engine chip. Said chip package was widely regarded to run at a clock speed of 4 GHz and with 32 APUs providing 32 GFLOPS each, the Broadband Engine was shown to have a teraflops of raw computing power. A patent is a set of exclusive rights granted by a government to an inventor or applicant for a limited amount of time (normally maximum 20 years from the filing date, depending on extension). ...

In March 2007 IBM announced that the 65 nm version of Cell BE is in production at its plant in East Fishkill, New York.^[13][14] The 65 nanometer (65 nm) process is the next milestone as of 2005 in semiconductor manufacturing and fabrication. ... East Fishkill is a town located in Dutchess County, New York. ... NY redirects here. ...

Commercialization

Please help improve this article or section by expanding it. Further information might be found on the talk page or at requests for expansion. This article has been tagged since January 2007.

On May 17, 2005, Sony Computer Entertainment confirmed some specifications of the Cell processor that would be shipping in the forthcoming PlayStation 3 console.^[15][16][17] This Cell configuration will have one Power processing element (PPE) on the core, with eight physical SPEs in silicon.^[17] In the PlayStation 3, one SPE is locked-out during the test process, a practice which helps to improve manufacturing yields.^[18] The target clock-frequency at introduction is 3.2 GHz.^[16] The introductory design is fabricated using a 90-nanometre SOI process, with initial volume production slated for IBM's facility in East Fishkill, New York.^[13] Image File history File links This is a lossless scalable vector image. ... is the 137th day of the year (138th in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... PlayStation 3 , trademarked PLAYSTATION®3,[7] commonly abbreviated PS3) is Sony Computer Entertainments third video game console. ... A gigahertz is a billion hertz or a thousand megahertz, a measure of frequency. ... A nanometre (American spelling: nanometer, symbol nm) is a unit of length in the metric system, equal to one thousand-millionth of a metre, which is the current SI base unit of length. ... Silicon on insulator (SOI) is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or silicon with an insulating layer of silicon dioxide(SiO2) 80 nm to 3 µm thick on its... East Fishkill is a town located in Dutchess County, New York. ... NY redirects here. ...

Note that the relationship between cores and threads is a common source of confusion. The PPE core is dual threaded and manifests in software as two independent threads of execution while each active SPE manifests as a single thread. In the PlayStation 3 configuration as described by Sony, the Cell processor provides nine independent threads of execution. This article or section does not adequately cite its references or sources. ... A thread in computer science is short for a thread of execution. ... Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of the hardware that executes instructions in a computer. ...

On June 28, 2005, IBM and Mercury Computer Systems announced a partnership agreement to build Cell-based computer systems for embedded applications such as medical imaging, industrial inspection, aerospace and defense, seismic processing, and telecommunications.^[19] Mercury has since then released blades, conventional rack servers and PCI Express accelerator boards with Cell processors.^[19] June 28 is the 179th day of the year (180th in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... Mercury Computer Systems, Inc. ... It has been suggested that Embedded System Design in an FPGA be merged into this article or section. ... Medical imaging designates the ensemble of techniques and processes used to create images of the human body (or parts thereof) for clinical purposes (medical procedures seeking to reveal, diagnose or examine disease) or medical science (including the study of normal anatomy and function). ... Look up aerospace in Wiktionary, the free dictionary. ... In military science, defense (or defence) is the art of preventing an enemy from conquering territory. ... Seismic reflection data Reflection seismology (or seismic reflection) is a method of exploration geophysics that uses the principles of seismology to estimate the properties of the Earths subsurface from reflected seismic waves. ... Telecommunication involves the transmission of signals over a distance for the purpose of communication. ... Equipment mounted in several 19-inch racks. ... PCI Express (formerly known as 3GIO for 3rd Generation I/O, not to be mistaken with PCI-X) is an implementation of the PCI computer bus that uses existing PCI programming concepts and communications standards, but bases it on a much faster serial communications system. ...

In the fall of 2006 IBM released the QS20 blade module using double Cell BE processors for tremendous performance in certain applications, reaching a peak of 410 gigaFLOPS per module. These modules are expected to be a part of the IBM Roadrunner supercomputer that will be operational in 2008. Mercury and IBM uses the fully utilized Cell processor with 8 active SPEs. It has been suggested that this article or section be merged into Blade server. ... In computing, FLOPS (or flops) is an acronym meaning FLoating point Operations Per Second. ... Roadrunner is the name given to a next-generation supercomputer to be built at the Los Alamos National Laboratory in New Mexico. ...

Overview

A Cell Processor

The Cell Broadband Engine—or Cell as it is more commonly known—is a microprocessor designed to bridge the gap between conventional desktop processors (such as the well known Pentium and PowerPC families) and more specialized high-performance processors, such as nVIDIA and ATI graphics-processors (GPUs). The name indicates its intended use, namely as a component in current and future digital distribution systems; as such it may be utilized in high-definition displays and recording equipment, as well as computer entertainment systems for the HDTV era. Additionally the processor should be well suited to digital imaging systems (medical, scientific, etc.) as well as physical simulation (e.g. scientific and structural engineering modeling). Image File history File links No higher resolution available. ... Image File history File links No higher resolution available. ... The Pentium is a fifth-generation x86 architecture microprocessor from Intel. ... PowerPC is a RISC microprocessor architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. ... NVIDIA Corporation (NASDAQ: NVDA) (pronounced ) is an American corporation specializing in the manufacture of GPU technologies for video cards, graphics cards, workstations, desktop computers, handhelds and more. ... ATI may stand for: ATI Technologies Inc. ... It has been suggested that this article be split into multiple articles. ... Digital distribution (Also known as digital delivery) is the principle of providing digital information and content over the Internet in the form of products or services. ... Projection screen in a home theater, displaying a high-definition television image. ... Digital imaging or digital image acquisition is the creation of digital images, typically from a physical object. ... Dynamical simulation, in computational physics, is the simulation of systems of objects that are free to move, usually in three dimensions according to Newtons laws of dynamics, or approximations thereto. ... Taipei 101, the worlds tallest building as of 2004. ...

In a simple analysis the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE) (a two-way SMT Power 970 architecture compliant core), eight fully-functional co-processors called the Synergistic Processing Elements or SPEs and a specialized high-bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB. Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of the hardware that executes instructions in a computer. ...

To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding MPEG streams, generating or transforming three dimensional data, or undertaking Fourier analysis of data, the Cell processor simply marries the SPEs and the PPE via the EIB to give both access to main memory or other external data storage. The PPE which is capable of running a conventional operating system has control over the SPEs and can start, stop, interrupt and schedule processes running on the SPEs. To this end the PPE has additional instructions relating to control of the SPEs. Despite having Turing complete architectures the SPEs are not fully autonomous and require the PPE to initiate them before they can do any useful work. Most of the "horsepower" of the system comes from the synergistic processing elements. The Moving Picture Experts Group or MPEG is a working group of ISO/IEC charged with the development of video and audio encoding standards. ... Harmonic analysis is the branch of mathematics which studies the representation of functions or signals as the superposition of basic waves. ... In computability theory a programming language or any other logical system is called Turing-complete if it has a computational power equivalent to a universal Turing machine. ...

The PPE and bus architecture includes various modes of operation giving different levels of memory protection, allowing areas of memory to be protected from access by specific processes running on the SPEs or PPE. Memory protection is a system that prevents one process from corrupting the memory of another process running on the same computer at the same time. ...

Both the PPE and SPE are RISC architectures with a fixed-width 32-bit instruction format. The PPE contains a 64-bit general purpose register set (GPR), a 64-bit floating point register set (FPR), and a 128-bit Altivec register set. The SPE contains 128-bit registers only. These can be used for scalar data types ranging from 8-bits to 128-bits in size or for SIMD computations on a variety of integer and floating point formats. System memory addresses for both the PPE and SPE are expressed as 64-bit values for a theoretic address range of 2⁶⁴ bytes. In practice, not all of these bits are implemented in hardware; the address space is extremely large nevertheless. Local store addresses internal to the SPU processor are expressed as a 32-bit word. In documentation relating to Cell a word is always taken to mean 32 bits, a doubleword means 64 bits, and a quadword means 128 bits. Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... In computer architecture, a processor register is a small amount of very fast computer memory used to speed the execution of computer programs by providing quick access to commonly used values—typically, the values being in the midst of a calculation at a given point in time. ... AltiVec is a floating point and integer SIMD instruction set designed and owned by Apple Computer, IBM and Motorola (the AIM alliance), and implemented on versions of the PowerPC including Motorolas G4 and IBMs G5 processors. ... -1...

Influence and contrast

In some ways the Cell system resembles early Seymour Cray designs in reverse. The famed CDC 6600 used a single very fast processor to handle the mathematical calculations, while a series of ten slower systems were given smaller programs to keep the main memory fed with data. In the Cell the problem has been reversed: reading the data is no longer the difficult problem due to the complex encodings used in industry; today the problem is efficiently decoding that data into an ever-less-compressed version as quickly as possible. Seymour Roger Cray (September 28, 1925 â€“ October 5, 1996) was a U.S. electrical engineer and supercomputer architect who founded the company Cray Research. ... The CDC 6600 was a mainframe computer from Control Data Corporation, first manufactured in 1965. ... Primary storage is a category of computer storage, often called main memory. ...

Modern graphics cards have multiple elements very similar to the SPEs, known as shader units, with an attached high speed memory. Programs, known as shaders, are loaded onto the units to process the input data streams fed from the previous stages (possibly the CPU), according to the required operations. A graphics/video/display card/board/adapter is a computer component designed to convert the logical representation of visual information into a signal that can be used as input for a display medium. ... In 3D computer graphics, a shader is a program used to determine the final surface properties of an object or image. ... Die of an Intel 80486DX2 microprocessor (actual size: 12×6. ...

The main differences are that the Cell's SPEs are much more general purpose than shader units, and the ability to chain the SPEs under program control offers considerably more flexibility, allowing the Cell to handle graphics, sound, or any other workload.

Architecture

Main article: Cell architecture

While the Cell chip can have a number of different configurations, the basic configuration is composed of one "Power Processor Element" ("PPE") (sometimes called "Processing Element", or "PE"), and multiple "Synergistic Processing Elements" ("SPE").^[20] The PPE and SPEs are linked together by an internal high speed bus dubbed "Element Interconnect Bus" ("EIB"). Due to the nature of its applications, Cell is optimized towards single precision floating point computation. The SPEs are capable of performing double precision calculations, albeit with an order of magnitude performance penalty. However, there are ways to circumvent this in software using iterative refinement, which means only the values are calculated in double precision when necessary. Jack Dongarra and his team demonstrated a 3.2 GHz Cell with 8 SPEs delivering a performance equal to 100 GFLOPS on an average double precision Linpack 4096x4096 matrix. Cell architecture Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. ... In computing, single precision is a computer numbering format that occupies one storage locations in computer memory at address. ... A floating-point number is a digital representation for a number in a certain subset of the rational numbers, and is often used to approximate an arbitrary real number on a computer. ... In computing, double precision is a computer numbering format that occupies two storage locations in computer memory at address and address+1. ... Jack Dongarra is a University Distinguished Professor of Computer Science in the Computer Science Department [1] at the University of Tennessee. ... LINPACK is a software library for performing numerical linear algebra on digital computers. ...

Power Processor Element

The PPE is the Power Architecture based, two-way multithreaded core acting as the controller for the eight SPEs, which handle most of the computational workload. The PPE will work with conventional operating systems due to its similarity to other 64-bit PowerPC processors, while the SPEs are designed for vectorized floating point code execution. The PPE contains a 32 KiB instruction and a 32 KiB data Level 1 cache and a 512 KiB Level 2 cache. Additionally, IBM has included a AltiVec unit^[21] which is fully pipelined for double precision floating point and each PPU can complete two double precision operations per clock cycle, which translates to 6.4 GFLOPS at 3.2 GHz; or eight single precision operations per clock cycle, which translates to 25.6 GFLOPS at 3.2 GHz.^[22] The Power Architecture logo Power Architecture is a broad term to describe similar instruction sets for RISC microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi. ... Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of the hardware that executes instructions in a computer. ... According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ... According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ... Look up cache in Wiktionary, the free dictionary. ... AltiVec is a floating point and integer SIMD instruction set designed and owned by Apple Computer, IBM and Motorola (the AIM alliance), and implemented on versions of the PowerPC including Motorolas G4 and IBMs G5 processors. ... In computing, double precision is a computer numbering format that occupies two storage locations in computer memory at address and address+1. ... ...

Synergistic Processing Elements (SPE)

Each SPE is composed of a "Synergistic Processing Unit", SPU, and a "Memory Flow Controller", MFC (DMA, MMU, and bus interface).^[23] An SPE is a RISC processor with 128-bit SIMD organization^[21][24][25] for single and double precision instructions. With the current generation of the Cell, each SPE contains a 256 KiB instruction and data local memory area (called "local store") which is visible to the PPE and can be addressed directly by software. Each SPE can support up to 4 GiB of local store memory. The local store does not operate like a conventional CPU cache since it is neither transparent to software nor does it contain hardware structures that predict which data to load. The SPEs contain a 128 × 128 register file and measure 14.5 mm² on a 90 nm process. An SPE can operate on 16 8-bit integers, 8 16-bit integers, 4 32-bit integers, or 4 single precision floating-point numbers in a single clock cycle. It can also do a memory operation in the same clock cycle. Note that the SPU processor cannot directly access system memory; the 64-bit memory addresses formed by the SPU must be passed from the SPU processor to the SPE memory flow controller (MFC) to set up a DMA operation within the system address space. Sebi saysDirect memory access (DMA) is a feature of modern computers, that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. ... This 68451 MMU could be used with the Motorola 68010 MMU, short for memory management unit or sometimes called paged memory management unit as PMMU, is a class of computer hardware components responsible for handling memory accesses requested by the CPU. Among the functions of such devices are the translation... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... In computer architecture, 128-bit integers, memory addresses, or other data units are those that are at most 128 bits wide. ... -1... According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ... There are very few or no other articles that link to this one. ... The term gib may refer to: a castrated male cat or ferret an abbreviation for gibibyte (GiB) or gibibit (Gib) an abbreviation for Gibraltar an abbreviation for Gib Board, itself an abbreviation of Gibraltar Board, all Winston Wallboards[1] tradenames for drywall (plasterboard). ... Look up cache in Wiktionary, the free dictionary. ... A register file is an array of processor registers in a central processing unit (CPU). ...

In one typical usage scenario, the system will load the SPEs with small programs (similar to threads), chaining the SPEs together to handle each step in a complex operation. For instance, a set-top box might load programs for reading a DVD, video and audio decoding, and display, and the data would be passed off from SPE to SPE until finally ending up on the TV. Another possibility is to partition the input data set and have several SPEs performing the same kind of operation in parallel. At 3.2 GHz, each SPE gives a theoretical 25.6 GFLOPS of single precision performance. A thread in computer science is short for a thread of execution. ... The term set-top box (STB) describes a device that connects to a television and some external source of signal, and turns the signal into content then displayed on the screen. ... ...

Compared to a modern personal computer, the relatively high overall floating point performance of a Cell processor seemingly dwarfs the abilities of the SIMD unit in desktop CPUs like the Pentium 4 and the Athlon 64. However, comparing only floating point abilities of a system is a one-dimensional and application-specific metric. Unlike a Cell processor, such desktop CPUs are more suited to the general purpose software usually run on personal computers. In addition to executing multiple instructions per clock, processors from Intel and AMD feature branch predictors. The Cell is designed to compensate for this with compiler assistance, in which prepare-to-branch instructions are created. For double-precision, as often used in personal computers, Cell performance drops by an order of magnitude, but still reaches 14 GFLOPS. New Intel Pentium 4 with Hyper Threading logo The Pentium 4 is a seventh-generation x86 architecture microprocessor produced by Intel and was the companys first all-new CPU design since the Pentium Pro of 1995. ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003[1]. It is the third processor to bear the name Athlon, and the immediate successor to the Athlon XP[2]. The second processor (after the Opteron) to implement AMD64 architecture and the... In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ...

Recent tests by IBM show that the SPEs can reach 98% of their theoretical peak performance using optimized parallel Matrix Multiplication.^[22]

Element Interconnect Bus (EIB)

The EIB is a communication bus internal to the Cell processor which connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants. The EIB also includes an arbitration unit which functions as a set of traffic lights. In some documents IBM refers to EIB bus participants as 'units'.

The EIB is presently implemented as a circular ring comprised of four 16B-wide unidirectional channels which counter-rotate in pairs. When traffic patterns permit, each channel can convey up to three transactions concurrently. As the EIB runs at half the system clock rate the effective channel rate is 16 bytes every two system clocks. At maximum concurrency, with three active transactions on each of the four rings, the peak instantaneous EIB bandwidth is 96B per clock (12 concurrent transactions * 16 bytes wide / 2 system clocks per transfer). While this figure is often quoted in IBM literature it is unrealistic to simply scale this number by processor clock speed. The arbitration unit imposes additional constraints which are discussed in the Bandwidth Assessment section below.

IBM Senior Engineer David Krolak, EIB lead designer, explains the concurrency model:

A ring can start a new op every three cycles. Each transfer always takes eight beats. That was one of the simplifications we made, it's optimized for streaming a lot of data. If you do small ops, it does not work quite as well. If you think of eight-car trains running around this track, as long as the trains aren't running into each other, they can coexist on the track.^[26]

Each participant on the EIB has one 16B read port and one 16B write port. The limit for a single participant is to read and write at a rate of 16B per EIB clock (for simplicity often regarded 8B per system clock). Note that each SPU processor contains a dedicated DMA management queue capable of scheduling long sequences of transactions to various endpoints without interfering with the SPU's ongoing computations; these DMA queues can be managed locally or remotely as well, providing additional flexibility in the control model.

Data flows on an EIB channel stepwise around the ring. Since there are twelve participants, the total number of steps around the channel back to the point of origin is twelve. Six steps is the longest distance between any pair of participants. An EIB channel is not permitted to convey data requiring more than six steps; such data must take the shorter route around the circle in the other direction. The number of steps involved in sending the packet has very little impact on transfer latency: the clock speed driving the steps is very fast relative to other considerations. However, longer communication distances are detrimental to the overall performance of the EIB as they reduce available concurrency.

Despite IBM's original desire to implement the EIB as a more powerful cross-bar, the circular configuration they adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole. In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels.

David Krolak explains:

Well, in the beginning, early in the development process, several people were pushing for a crossbar switch, and the way the bus is architected, you could actually pull out the EIB and put in a crossbar switch if you were willing to devote more silicon space on the chip to wiring. We had to find a balance between connectivity and area, and there just was not enough room to put a full crossbar switch in. So we came up with this ring structure which we think is very interesting. It fits within the area constraints and still has very impressive bandwidth.^[26]

Bandwidth assessment

For the sake of quoting performance numbers, we will assume a Cell processor running at 3.2 GHz, the clock speed most often cited.

At this clock frequency each channel flows at a rate of 25.6 GB/s. Viewing the EIB in isolation from the system elements it connects, achieving twelve concurrent transactions at this flow rate works out to an abstract EIB bandwidth of 307.2 GB/s. Based on this view many IBM publications depict available EIB bandwidth as "greater than 300 GB/s". This number reflects the peak instantaneous EIB bandwidth scaled by processor frequency.^[27]

However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explains:

Each unit on the EIB can simultaneously send and receive 16B of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in the system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128B, the theoretical peak data bandwidth on the EIB at 3.2 GHz is 128Bx1.6 GHz = 204.8 GB/s.^[22]

This quote apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in the documentation set as yet made public by IBM.

In practice effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6 GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6 GB/s for reads and writes combined and the two IO controllers are documented as supporting a peak combined input speed of 25.6 GB/s and a peak combined output speed of 35 GB/s.

To add further to the confusion, some older publications cite EIB bandwidth assuming a 4 GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384 GB/s and an arbitration-limited bandwidth figure of 256 GB/s.

All things considered the theoretic 204.8 GB/s number most often cited is the best one to bear in mind. The IBM Systems Performance group has demonstrated SPU-centric data flows achieving 197 GB/s on a Cell processor running at 3.2 GHz so this number is a fair reflection on practice as well.

Optical Interconnect

Sony is currently working on the development of an optical interconnection technology for use in the device-to-device or internal interface of various types of cell-based digital consumer electronics and game systems.

Memory controller and I/O

Cell contains a dual channel next-generation Rambus XIO macro which interfaces to Rambus XDR memory. The memory interface controller (MIC) is separate from the XIO macro and is designed by IBM. The XIO-XDR link runs at 3.2 Gbit/s per pin. Two 32 bit channels can provide a theoretical maximum of 25.6 GB/s. This article is about the company. ...

The system interface used in Cell, also a Rambus design, is known as FlexIO. The FlexIO interface is organized into 12 "lanes," each lane being a unidirectional 8-bit wide point-to-point path. Five 8-bit wide point-to-point paths are inbound lanes to Cell, while the remaining seven are outbound. This provides a theoretical peak bandwidth of 62.4 GB/s (36.4 GB/s outbound, 26 GB/s inbound) at 2.6 GHz. The FlexIO interface can be clocked independently, typ. at 3.2 GHz. 4 inbound + 4 outbound lanes are supporting memory coherency.

Possible applications

Main article: Cell microprocessor implementations

// IBM has published information concerning two different versions of Cell in this process, an early engineering sample designated DD1, and an enhanced version designated DD2 intended for production. ...

Blade Server

IBM has presented the QS20 blade server based on two Cell processors, originally running the 2.6.11 Linux kernel.^[28] The prototypes ran at 2.4 GHz. Current systems run at 3.2 GHz, providing 205 GFLOPS single-precision floating point performance per CPU (or 410 GFLOPS per board). IBM also expects to arrange seven blades in a single rackmount chassis (similar to their BladeCenter product line) for a total performance of 2.8 TFLOPS (or 284 GFLOPS in double precision) per chassis. However, the performance numbers released by IBM are still theoretical, and the real-world performance could be significantly different from theoretical expectations. IBM HS20 blade server. ... The Linux kernel is a Unix-like operating system kernel. ... ... ... In computing, FLOPS is an abbreviation of floating point operations per second. ...

Mercury Computer Systems, Inc. has released blades, conventional rack servers and PCI Express accelerator boards with Cell processors. Mercury Computer Systems, Inc. ... Equipment mounted in several 19-inch racks. ... PCI Express (formerly known as 3GIO for 3rd Generation I/O, not to be mistaken with PCI-X) is an implementation of the PCI computer bus that uses existing PCI programming concepts and communications standards, but bases it on a much faster serial communications system. ...

Console Videogames

Sony's PlayStation 3 video game console contains the first production application of the Cell processor, clocked at 3.2 GHz and containing seven out of eight operational SPEs, to allow Sony to increase the yield on the processor manufacture. Only six of the seven SPEs are accessible to developers as one is reserved by the OS.^[18] Sony Corporation ) is a Japanese multinational corporation and one of the worlds largest media conglomerates with revenue of $68. ... PlayStation 3 , trademarked PLAYSTATION®3,[7] commonly abbreviated PS3) is Sony Computer Entertainments third video game console. ... Four different video game consoles from different generations. ... A gigahertz is a billion hertz or a thousand megahertz, a measure of frequency. ... Nasas Glenn Research Center clean room. ...

Home Cinema

Reportedly, Toshiba is considering producing HDTVs using Cell. They have already presented a system to decode 48 MPEG-2 streams simultaneously on a 1920×1080 screen.^[29][30] This can enable a viewer to choose a channel based on dozens of thumbnail videos displayed simultaneously on the screen. Projection screen in a home theater, displaying a high-definition television image. ... MPEG-2 is a standard for the generic coding of moving pictures and associated audio information [1]. It is widely used around the world to specify the format of the digital television signals that are broadcast by terrestrial (over-the-air), cable, and direct broadcast satellite TV systems. ... 1080i is shorthand name for a category of video modes. ...

Supercomputing

IBM's new planned supercomputer, IBM Roadrunner, will be a hybrid of General Purpose CISC as well as Cell processors. It is reported that this combination will produce the first computer to run at petaflop speeds. It will use an updated version of the Cell processor, manufactured using 65 nm technology and enhanced SPUs that can handle double precision calculations in the 128 bit registers, reaching double precision 100 GFLOPs.^[31][32] Roadrunner is the name given to a next-generation supercomputer to be built at the Los Alamos National Laboratory in New Mexico. ... ...

Cluster Computing

Clusters of PlayStation 3 consoles are an attractive alternative to high-end systems based on Cell blades. Innovative Computing Laboratory, a group led by Jack Dongarra, in the Computer Science Department at the University of Tennessee, investigated such an application in depth.^[33] PlayStation 3 , trademarked PLAYSTATION®3,[7] commonly abbreviated PS3) is Sony Computer Entertainments third video game console. ... Jack Dongarra is a University Distinguished Professor of Computer Science in the Computer Science Department [1] at the University of Tennessee. ...

Mainframes

IBM announced April 25, 2007 that it will begin integrating its Cell Broadband Engine Architecture microprocessors into the company's line of mainframes.^[34]

Software engineering

Main article: Cell software development

Due to the flexible nature of the Cell, there are several possibilities for the utilization of its resources:^[35] Software development for the cell microprocessor involve a mixture of conventional development practices for the POWER architecture-compatible PPU core, and novel software development challenges with regards to the functionally reduced SPU coprocessors. ...

Job queue

The PPE maintains a job queue, schedules jobs in SPEs, and monitors progress. Each SPE runs a "mini kernel" whose role is to fetch a job, execute it, and synchronize with the PPE.

Self-multitasking of SPEs

The kernel and scheduling is distributed across the SPEs. Tasks are synchronized using mutexes or semaphores as in a conventional operating system. Ready-to-run tasks wait in a queue for a SPE to execute them. The SPEs use shared memory for all tasks in this configuration. Mutual exclusion (often abbreviated to mutex) algorithms are used in concurrent programming to avoid the simultaneous use of un-shareable resources by pieces of computer code called critical sections. ... A semaphore is a protected variable (or abstract data type) and constitutes the classic method for restricting access to shared resources (e. ... // An operating system (OS) is a set of computer programs that manage the hardware and software resources of a computer. ...

Stream processing

Each SPE runs a distinct program. Data comes from an input stream, and is sent to SPEs. When an SPE has terminated the processing, the output data is sent to output stream.

This provides a flexible and powerful architecture for stream processing, and allows explicit scheduling for each SPE separately. Other processors are also able to perform streaming tasks, but are limited by the kernel loaded. It has been suggested that GPGPU be merged into this article or section. ...

Open source software development

In 2005, patches enabling Cell support in the Linux kernel were submitted for inclusion by IBM developers.^[36] Arnd Bergmann (one of the developers of the aforementioned patches) also described the Linux-based Cell architecture at LinuxTag 2005.^[37] 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... LinuxTag (or more formally ) is a Free Software expo held every summer in the town of Karlsruhe in southern Germany. ...

Both PPE and SPEs are programmable in C/C++ using a common API provided by libraries. According to Sony, a compiler, debugger, IDE, performance analyzer, and Cell emulator should be made available soon.^[35] IBM has developed a pseudo-filesystem for Linux coined "Spufs" that simplifies access to and use of the SPE resources. IBM is currently maintaining the Linux kernel and GDB ports, while Sony maintains the GNU toolchain (GCC, binutils).^[38] A kernel connects the application software to the hardware of a computer. ... The GNU Debugger, usually called just GDB, is the standard debugger for the GNU software system. ... The GNU toolchain is a blanket term given to the programming tools produced by the GNU project. ... The GNU Compiler Collection (usually shortened to GCC) is a set of programming language compilers produced by the GNU Project. ... The GNU Binutils is a collection of programming tools developed by the Free Software Foundation for the manipulation of object code in various object file formats. ...

In November 2005, IBM released a "Cell Broadband Engine (CBE) Software Development Kit Version 1.0", consisting of a simulator and assorted tools, to its web site. Development versions of the latest kernel and tools for Fedora Core 4 are maintained at the Barcelona Supercomputing Center website.^[39] Fedora Core is an RPM-based Linux distribution, developed by the community-supported Fedora Project and sponsored by Red Hat. ... The building of Barcelona Supercomputing Center is a former chapel. ...

With the release of kernel version 2.6.16 on March 20, 2006, the Linux kernel officially supports the Cell processor.^[40] March 20 is the 79th day of the year in the Gregorian Calendar (80th in leap years). ... For the Manfred Mann album, see 2006 (album). ...

Abbreviations

EIB

Element Interconnect Bus^[41]

LS

Local Storage (SPE's local memory)^[42]

MIC

Memory Interface Controller^[41]

PPE

Power Processor Element^[41]

SMF

Synergistic Memory Flow Controller

SPE

Synergistic Processing Element^[41]

SPU

Streaming Processor Unit^[43]

STI

Sony Computer Entertainment Inc., Toshiba Corp., IBM

Layout of the IBM Cell die Cell is a microprocessor architecture jointly developed by a Sony, Toshiba, and IBM, an alliance known as STI. The architectural design and first implementation were carried out at the STI Design Center over a four-year period beginning March 2001 on a budget reported... Layout of the IBM Cell die Cell is a microprocessor architecture jointly developed by a Sony, Toshiba, and IBM, an alliance known as STI. The architectural design and first implementation were carried out at the STI Design Center over a four-year period beginning March 2001 on a budget reported... Layout of the IBM Cell die Cell is a microprocessor architecture jointly developed by a Sony, Toshiba, and IBM, an alliance known as STI. The architectural design and first implementation were carried out at the STI Design Center over a four-year period beginning March 2001 on a budget reported...

See also

• IBM POWER
• Other MIMD-on-a-chip processors ( Multi-core processors) include
  • TMS320C80 MVP (multimedia video processor)
  • Kilocore
  • Emotion Engine
  • graphics processing unit
  • the Parallax Propeller
  • sometimes multiple CPUs are placed on a single FPGA
• Apulet

POWER is a RISC instruction set architecture designed by IBM. The name is a acronym for Performance Optimization With Enhanced RISC. POWER is also the name of a series of microprocessors that implements the instruction set architecture. ... Multiple Instruction Multiple Data (MIMD) is a type of parallel computing architecture where many functional units perform different operations on different data. ... This article or section does not adequately cite its references or sources. ... Texas Instruments TMS320 is a blanket name for a series of digital signal processors from Texas Instruments. ... Kilocore, from Rapport Inc. ... Sony Emotion Engine CPU The Emotion Engine is the name of the Central Processing Unit (CPU) used in Sony PlayStation 2 video game consoles. ... It has been suggested that this article be split into multiple articles. ... The Parallax Propeller, or P8X32 as this is its official designator, is a multiprocessor microcontroller with eight 32bit RISC CPU cores. ... A field-programmable gate array or FPGA is a gate array that can be reprogrammed after it is manufactured, rather than having its programming fixed during the manufacturing — a programmable logic device. ... An apulet (plural apulettes) is a component of the Cell computer architecture consisting of a bundle comprising a data object and the code necessary to perform an action upon it. ...

References

Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 116th day of the year (117th in leap years) in the Gregorian calendar. ... For the Manfred Mann album, see 2006 (album). ... February 22 is the 53rd day of the year in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 314th day of the year (315th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 77th day of the year (78th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... A news release, press release or press statement is a written or recorded communication directed at members of the news media for the purpose of announcing something claimed as having news value. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... For the Manfred Mann album, see 2006 (album). ... November 14 is the 318th day of the year (319th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... August 7 is the 219th day of the year (220th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... March 12 is the 71st day of the year (72nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... This article or section does not cite its references or sources. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... February 7 is the 38th day of the year in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... May 18 is the 138th day of the year (139th in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 137th day of the year (138th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 137th day of the year (138th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 102nd day of the year (103rd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... May 18 is the 138th day of the year (139th in leap years) in the Gregorian calendar. ... February 7 is the 38th day of the year in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... February 16 is the 47th day of the year in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... November 29 is the 333rd (in leap years the 334th) day of the year in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 96th day of the year (97th in leap years) in the Gregorian calendar. ... For the Manfred Mann album, see 2006 (album). ... June 11 is the 162nd day of the year (163rd in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... Mar, one of the ancient divisions or provinces of Scotland, comprised the larger portion of Aberdeenshire, extending from north of the Don southward to the Mounth. ... For the Manfred Mann album, see 2006 (album). ... November 1 is the 305th day of the year (306th in leap years) in the Gregorian Calendar, with 60 days remaining. ... For the Manfred Mann album, see 2006 (album). ... August 15 is the 227th day of the year in the Gregorian Calendar (228th in leap years), with 138 days remaining. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... January 1 is the first day of the calendar year in both the Julian and Gregorian calendars. ... For the Manfred Mann album, see 2006 (album). ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 77th day of the year (78th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... is the 145th day of the year (146th in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... April 25 is the 115th day of the year in the Gregorian calendar (116th in leap years). ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 1st day of the year in the Gregorian calendar. ... For the Manfred Mann album, see 2006 (album). ... October 25 is the 298th day of the year (299th in leap years) in the Gregorian calendar. ... For the Manfred Mann album, see 2006 (album). ... This article does not cite any references or sources. ... For the Manfred Mann album, see 2006 (album). ... May 8 is the 128th day of the year in the Gregorian calendar (129th in leap years). ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... eWeek:the Enterprise Newsweekly is a weekly magazine published by Ziff Davis Media, featuring editorials, reviews, labs and rumors. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 116th day of the year (117th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... May 18 is the 138th day of the year (139th in leap years) in the Gregorian calendar. ... March 9 is the 68th day of the year in the Gregorian calendar (69th in leap years). ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 172nd day of the year (173rd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... June 11 is the 162nd day of the year (163rd in leap years) in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... is the 176th day of the year (177th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... For the Manfred Mann album, see 2006 (album). ... March 21 is the 80th day of the year (81st in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 22 is the 81st day of the year (82nd in leap years) in the Gregorian calendar. ... February 8 is the 39th day of the year in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... February 10 is the 41st day of the year in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... February 9 is the 40th day of the year in the Gregorian calendar. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ...

External links

• Cell Broadband Engine resource center
• Standards and documentation
• Sony Computer Entertainment International's CELL resource page