Some digital data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop (PLL). This process is commonly known as clock and data recovery (CDR). Image File history File links Edit-copy_purple. ... Wikibooks logo Wikibooks, previously called Wikimedia Free Textbook Project and Wikimedia-Textbooks, is a wiki for the creation of books. ... Disk Drive is the afternoon show on CBC Radio Two. ... A phase-lock, or phase-locked, loop (PLL) is an electronic control system that generates a signal that is locked to the phase of an input or reference signal. ...

In order for this scheme to work, a data stream must transition frequently enough to correct for any drift in the PLL's oscillator. The limit for how long a clock recovery unit can operate without a transition is known as its maximum consecutive identical digits (CID) specification. To ensure frequent transitions, some sort of encoding is used; 8B/10B encoding is very common, while Manchester encoding serves the same purpose in old revisions of 802.3 local area networks. In telecommunications, 8b/10b is a line code that maps 8-bit symbols to 10-bit symbols to achieve DC-balance (see DC coefficient) and bounded disparity, and yet provide enough state changes to allow reasonable clock recovery. ... Encoding of 11011000100 in Manchester code In telecommunication, Manchester code is a form of data communications line code in which each bit of data is signified by at least one transition. ... IEEE 802. ... “LAN” redirects here. ...

Timing in (serial) Data transmission

In telecommunication, serial transmission is the sequential transmission of the signal elements of a group representing a character or other entity of data. ... Data transmission is the conveyance of any kind of information from one space to another. ...

Introduction

To transmit digital information along distances longer than the internal bus of a computer, it is necessary to serialise it and to encode together the bit stream and its clock. The resulting signal will travel and be less affected by the noise and the transfer function of the transmission medium. The data signal and its clock travel together and experience the very same delay. At the receiving end, the signal is equalised and the noise filtered out as much as possible. Then the timing information is extracted, and the bit stream regenerated. The action of recuperating the clock signal from the received signal is inevitably affected by some deterioration: the square wave extracted is not exactly synchronous with the transmit clock. Timing information, that is essentially carried by the level transitions of the received signal, has been affected by the noise and by the intersymbol interference and has acquired:

• some inevitable delay, due to the physical transit time, and to the extraction process,
• some inaccuracy (= phase modulation, called jitter)
• some errored bits with a (very) low probability, or –in other words- a bit error rate of very low value (e.g. < 10^-19 )

The jitter can be kept to a minimum with sophisticated clock extraction circuits, but not eliminated. On the other hand, in the network topology there are always points where signals that had been originated by the same clock and have cumulated different jitters along different transmission paths, must be put together again. To absorb the jitter differences an elastic buffer (i.e. a buffer memory) is used.
Note: a serialised transmission, with clock and data encoded together, becomes necessary when the bit rate and the wavelength at the bit rate frequency become comparable (when different paths travelled by parallel streams can be different by 25% or more of a wavelength). For example: at 1 Gbit/s the wavelength to refer to is: c/1 GHz = 3 * 10^8 m/s / 10^9 sec-1 = 30 cm. Considering that on PCB the speed is 60% lower than in vacuum, the reference distance is 60% of 30 cm, or about 20 cm. As a result, serial encoded transmission @ 1 Gbit/s becomes necessary when distance differences amongst parallel paths are 5 cm or more. The delay difference amongst different parallel paths causes bits, that have been sent at the same instant on different paths, to be received at different clock cycles of the clock at the receiving end. To put them back in sync, it is necessary to insert redundant bits inside each path, so that a frame sync can be detected. Then buffer memories on each path will be used to put back in sync all the bits of the parallel paths. Interfaces with this structure have been proposed, and are in use in some systems. In most practical applications though, the approach of serialising several parallel streams of bits (typically 8), with the multiplication of the clock frequency, has been found to be preferable to the alternative approach of adding the sync structure on each bit stream at the transmit end and to recover that, with use of buffer memories, at the receive end. In telecommunication, jitter is an abrupt and unwanted variation of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. ...

1. Buffer Memory (Elastic buffer)

In telecommunication, a buffer is a routine or storage medium used in telecommunications to compensate for a difference in rate of flow of data, or time of occurrence of events, when transferring data from one device to another. ... Image File history File links No higher resolution available. ...

1. Buffer Memory (Elastic buffer)

An adder compares the content of the two counters. In telecommunication, a buffer is a routine or storage medium used in telecommunications to compensate for a difference in rate of flow of data, or time of occurrence of events, when transferring data from one device to another. ...

At the start-up of the system, the write counter is set to 0, and the reading counter is set to half the memory depth. It is possible to program the initial value of the read counter to less than half the memory depth, to use less than the entire memory - thereby reducing the transit delay.

In general a buffer memory may be used to absorb delays, or just delay variations (jitter), generated by transmission over physical media, or by software elaboration, or other types of delays.

If designed to absorb delay variations due to the transit along a transmission line (that is: designed to absorb jitter), then its size in bytes (or in bits) is smaller, the control of the phase relation of the write and of the read clocks is more accurate, and its name specialises in “phase aligner”* or, more properly, into “elastic buffer”.

* more precisely: a phase aligner is an elastic buffer used inside a single clock domain.

OVERFLOW and UNDERFLOW

Two clocks that differ slightly in frequency (=wander) with respect to each other, or that jitter with respect to the one another, will -from time to time- change their respective positions cumulating more than one clock period change. The slower clock “slips” with respect to the other and the period that it loses is a “slip”. In telecommunication, wander are long-term random variations of the significant instants of a digital signal from their ideal positions. ...

When the reading (reading clock faster than the writing clock) takes place synchronously or before the corresponding writing cycle, then an underflow occurs (with a repetition of some information elements).

If instead this condition is approached because the reading clock is too slow with respect to the writing clock, then an overflow occurs (and some information elements are skipped = cancelled).

In case of over/underflow, the reading counter is reinitialised, half a memory behind the write clock (to restart with the maximum margin against another future occurrence).

If instead this condition is approached because the reading clock is too slow with respect to the writing clock, then an overflow occurs (and some information elements are skipped = cancelled). Figure 2 above shows a case where two different clocks (the system clock and its copy after many regenerations) are to be re-synchronised together. This is not the most general case, because the two clocks represented here belong to the same clock domain (i.e. are generated from the same clock, apart from fixed delay and jitter). If two clocks that do not share a link with a common clock source (=they belong to different clock domains) and are to be reconciled (by an elastic buffer), then the thing is complicated by the fact that, in addition to jitter, they exhibit a frequency difference (a wander), although small. Image File history File links No higher resolution available. ... In telecommunication, wander are long-term random variations of the significant instants of a digital signal from their ideal positions. ...

If an elastic buffer, of depth equal to n clock cycles, is at the boundary between different clock domains of frequencies f1 and f1-Δf, it will be subject to periodic slips (under or overflows), with a frequency given by:

• Deliberate Slips (overflow or underflow execution with minimum inconvenience to the “payload”)

In some cases, when the incoming data flow is framed, if a slip is inevitable it may be convenient to slip (cancel or replicate) an entire frame, exactly from beginning to end (e.g. TDM frames of layer 1 synchronization).

Or, if the incoming data have a layer 2 packet structure, it may be convenient to drop or duplicate inter-frame idle characters (e.g. Ethernet inter-frame characters).

To do so, when the reading clock gets close (e.g. within +/- 5% of the buffer size) to the writing clock and a slip appears inevitable within a short time, the decision to slip is taken, but it is put to effect a little later, in coincidence with the start of the next frame. Obviously, the buffer must be long at least 10% more than one entire frame.

The cost is not significantly different if the buffer memory is organised by bit or by byte. The saving in transit time when organising by bit with respect to organising by byte, is not significant either, as the average delay is expected to be several bytes.

TRANSIT DELAY inside the elastic buffer

The elastic buffer essential function is to add a delay to the information stream that, added to the jittered delay in the incoming stream, makes the total delay a fixed amount:

• first the additional delay is calculated
• and then it is added.

In this way the clock received can be made again synchronous to the clock that originated it (or -more generally- to a clock that has followed a different path and cumulated a different jitter).
As Figure 2 above indicates, the buffer memory (or elastic buffer, that is a name more indicated when the memory accomplishes the task of adding such complementary delay) is a delay line.
The bit stream enters with the transmission line clock obtained after several regenerations, is delayed by the necessary amount, and gets out with the system clock: the bit stream (and in several cases also the byte or frame synchronisation) is again perfectly synchronous with the system timings.
In many cases the elastic buffer is written with blocks of bits at every write operation, and discharged by the same amount of bit at every read operation. In this case the frequency of the write and of the read clock is a corresponding submultiple of the transmission line clock and of the system clock.
In practice the write and read cycle treat an entire byte or an entire frame at each time. The byte or the frame sync is embedded in the bit stream by the addition at the transmit end of some redundancy bits with a pattern that be at the same time difficult to simulate by the information bits and easy to recognize at the receive end.
The sync timing is detected at the receive end and can also be used for the write and read operations of the elastic buffer.
It should also be noted that an elastic buffer is sometimes built by several sections that operate on parallel bit streams received. One example can be the re-sync of truly parallel streams of bits received from a parallel interface, another can be the multiple sampling of a received pulse in a serial transmission for subsequent processing in a DSP.
It is important to understand that, inside the elastic buffer, the information of how much delay the buffer memory is adding in any given moment is available.
This point may be relevant when –for instance- it is necessary to measure the transmission line length measuring the transit time. Iin such case the time spent during the transit throughout the elastic buffer must be deducted.
For instance, let's consider the delay that the signal suffers along the last span of the transmission line in Figure 2. It is easy to measure the total delay in periods of the system clock ( but it will be inclusive of the delay added by the elastic buffer). Then the delay of the elastic buffer shall be deducted, and the transmission delay exactly computed. The term DSP, when used by itself, can refer to: // Underground Bhangra DJ Short for Deathlike Silence Productions. ...

Clock and Data Recovery for baseband line codes

At the receiving end of a data transmission link, the received signal is amplified, filtered and equalized. Then the embedded clock signal is extracted and can be used to regenerate the pulses of the received signal. The circuit that extracts the clock to allow the pulse regeneration is called CDR. The CDR, for signals without any line coding (NRZ = non-return-to-zero where every pulse of the signal is exactly one information bit of the transmitted stream), can be directly used to sample the incoming pulse stream to obtain the stream of regenerated information bits (no further decoding is necessary).
The clock recovery circuit (CDR) has -in all practical cases- the architecture of a Phase Locked Loop (PLL). An example of coding a binary signal using rectangular pulse amplitude modulation with polar non-return-to-zero code An example of Bipolar encoding, or AMI. Encoding of 11011000100 in Manchester encoding An example of Differential Manchester encoding An example of Biphase mark code An example of MLT-3 encoding. ... Contrast with: return-to-zero. ... Many electronic systems use internal clocks which are required to be phase-aligned to and/or frequency multiples of some external reference clock. ...

A phase comparator compares the phase information provided by the level transitions of the incoming signal, with the phase of a local clock. Its output is a signal proportional to the phase difference between the two phases. Image File history File links No higher resolution available. ... This article or section does not cite any references or sources. ...

The output of the comparator is used to correct the frequency of the local clock.

To achieve the desired transfer function, from the phase modulation present in the incoming signal to the residual phase modulation present in the output clock (the jitter transfer function), some low pass filtering is almost always added between the output of the phase comparator and the input that controls the frequency of the local clock. It may be noted that the local clock is controlled in its frequency, and that –as a consequence- the open loop transfer function includes the “integration” corresponding to the fact that the output phase of the local clock is the integral function of its input (as it is its frequency that is directly controlled). Another pole at zero frequency is normally present in the low pass filter. It has the main purpose to make the steady state phase error, between the phase of the incoming signal and the phase of the recovered clock, to be zero.

In practice, the PLL loops can be:

1. unconditionally stable = first order loop, large bandwidth, fast acquisition, with very good tracking but poor jitter filtering, and can either be:
   1. without filter block, or
   2. with filter (low pass) of the first order but with VCO that is controlled, by the filter output, in phase and not in frequency. Circuits of this type are sometimes called "phase aligners" and are used when fast acquisition and good tracking is required. This approach is possible when:
      1. the difference in frequency between the signal to lock and the frequency of the local oscillator is small
      2. the deviations in frequency of the local oscillator, when asked for repeated phase corrections of either polarity, is much larger than the difference in frequency between the signal to lock and its own center frequency;
2. with filter (low pass) of the first order = second order loop, unconditionally stable, narrow bandwidth, slow acquisition, the most common in transport applications; they offer good tracking of low jitter frequencies and good filtering of the high jitter frequencies;
3. with filter (low pass) of the second order = third order loop, less common because of their greater complexity and risk of instability.

Jitter Tolerance, Jitter Transfer Function and Generated Jitter

What are, in general, the different requirement of the extraction of the clock from an incoming (encoded) bit stream?
They are essentially 3:

• the ability to operate correctly (that is with a low enough BER) in presence of a given jitter. This is called Jitter Tolerance (or Jitter Acceptance), and is often specified as a mask of jitter amplitude versus jitter frequency. The circuit must operate correctly at any condition defined by a jitter amplitude and a jitter frquency within the boundary set by the mask. In other words, the locus of the conditions of onset of BER shall be measured and found above the boundary set by the mask
• the filtering of jitter frequencies above the frequency range involved in the lock-in and tracking. This is called Jitter Transfer Function, and is often a curve setting an upper limit for the curve that characterises our circuit (ratio at any given frequency of the amplitude of the jitter at the output and of the jitter at the input)
• the amount of Generated Jitter inside our circuit (phase noise added to the retrieved timing signal). Often specified as a rms or peak value of the output jitter with zero input jitter.

The ITU-T, in its Recommendations, is an invaluable source of theory and practical knowledge on the subject. It primarily deals with the requirements of large, geographical, networks, and therefore these Recommendations are especially useful, and exact in their quantitative references, for the engineer that studies Telecom digital networks, but they can also provide a lot of insight if other fields of application of CDRs are being targeted. Particularly interesting for the subject of this page are the Recommendations:

• G. 783
• G. 812
• G. 813
• G. 825.

More on the jitter theory and measurement

Mathematics for the classic reference model

Today' CDR circuits are implemented following a PLL architecture, and are realized mostly or entirely with CMos digital circuitry. The complexity of the circuitry is often so large that -not unfrequently- the architecture is not clearly identified and consequently the circuit operation is not fully understood. It is very useful to make reference to a relatively simple analog circuit that implements a CDR in a second order PLL architecture. The comprehension of its characteristics and of the mathematical equations that describe its behaviour are well suited to understand almost all the actual circuits and often even to allow a better design of them.

It should be noted that the study of the CDR system frequency response describes in actuality the behaviour in presence of sinusoidal jitter. Some periodicity in the bit stream due to framing may induce -via intersymbol interference- periodic components of jitter, but the real jitter will be essentially noisy. On the other hand, sinusoidal jitter represents the worst case jitter with respect to jitter tolerance and therefore sinusoidal jitter considerations give some margin with respect to the reality of the circuit application.

Mathematical description of a second order PLL circuit for CDR functions.

Block diagrams can be used to describe a physical system or the schematic diagram of it, or of the set of mathematical equations characterizing its parts. However, mathematical models, in the form of systems equations, are needed when detailed relationships are required.

Every control system may theoretically be characterized by mathematical equations. The solution of these equations represents the system’s behavior.
Often this solution is difficult if not impossible to find.
In these cases, certain simplifying assumptions must be made in the mathematical description. For a large number of control systems these approximations and simplifications lead to systems describable by linear ordinary differential equations. Moreover, techniques for solving these equations are well documented in the literature of mathematics and engineering.
In modern communication systems the implementation of the clock and data recovery circuits (CDR) is primarily digital, and the circuits can be very complex (in particular the loop filters and the local oscillator). The designer sometimes may find difficult to choose the right architecture and also to understand the operation of the circuit itself in some conditions.
The best way to solve this is to choose a system architecture basically corresponding to the structure of a second order analog phase locked loop, and to refer to the mathematical description of it to understand the closed loop operation in all conditions and to actually design the system circuitry blocks. Not only a second order PLL offers one of the best compromises possible between stability and performance, but it also can be well described mathematically and its operation understood. Once familiar with its operation, the circuit designer will be able and decide what circuit choices to make, in terms of structure of the blocks and even of the order of its PLL.

A linear, time-invariant idealization of the circuit will be therefore described here. The most common case of a second order loop will be presented. Although such idealization may not perfectly describe our circuit in some specific aspects (non-linearity of some circuit blocks, etc.) it serves to simplify the mathematics, keeps us from getting lost in a welter of algebraic quantities, and –most of all- produces results that can be interpreted quite usefully.

The functions that describe the relations amongst the variables shown in the figure, expressed for the sinusoidal jitter condition, are: Image File history File links Size of this preview: 800 × 367 pixelsFull resolution (807 × 370 pixel, file size: 16 KB, MIME type: image/png)By Pierandrea Borgato, from his own electronics knowledge Pierandrea Borgato 15:21, 26 August 2007 (UTC) File historyClick on a date/time to view the file...

The transfer function for a sinusoidal input (that is the Jitter Transfer function!)

Jitter transfer function

The magnitude of the jitter transfer function of jω tells, at each frequency f = ω/2π , the amplitude of the output jitter for an input jitter with the amplitude of 1 radian ≈ 57.3°.

The following figure is the Bode magnitude plot of the jitter transfer function. Curves for different values of the parameter ζ (damping ratio) are shown:

It can be seen that the CDR is essentially a low-pass filter, with no amplification of the input jitter but for values of the damping ratio greater than = 0.707 at some frquencies at and around the resonant frequency. The peak amplification occurs at and is: Image File history File links Size of this preview: 800 × 384 pixelsFull resolution (938 × 450 pixel, file size: 22 KB, MIME type: image/png) By Pierandrea Borgato Template:GFDL Pierandrea Borgato Pierandrea Borgato 14:02, 13 August 2007 (UTC) Permission is granted to copy, distribute and/or modify this document...

Error function

Another way of looking at the same critical frequency band of PLL tracking is to look at the function that describes the phase difference between output and input. First let's compute the complex function (output - input). Such function is itself a function of the same complex frequency. Its magnitude tells, at every jitter frequency, the amplitude of the sinusoidal distance between the output and the input phases. It is easy to realize that such function is the loop error function:

The following figure plots the magnitude of the error function. The y scale is in radian (1 radian ≈ 57.3°).

At low jitter frequencies there is practically no error, because the tracking is very good. At very high jitter frequencies the error is practically identical to the input: in fact the PLL is not able to track the jitter and the local clock stays unmoving with respect to it. At intermediate jitter frequencies, around f_n, the error increases with frequency till it is as large as the input jitter itself, or even up to the point of becoming larger than it at frequencies just above f_n for low values of ζ. Large values of ζ ( >> 1) involve a large error even at frequencies much lower than f_n, and small values of ζ ( < 0.7) correspond to large overshoots of the phase error just above f_n. values of ζ between 0.7 and 1.5 are therefore an inevitable design choice, but other considerations can be drawn from the study of the jitter tolerance function and suggest an even tighter range of ζ values for the CDR design. Image File history File links Size of this preview: 800 × 462 pixelsFull resolution (926 × 535 pixel, file size: 35 KB, MIME type: image/png) by Pierandrea Borgato Template:GFDL Pierandrea Borgato Pierandrea Borgato 15:40, 15 August 2007 (UTC) Permission is granted to copy, distribute and/or modify this document...

It can be noted that both the jitter transfer and the jitter error functions are true "transfer functions". They tell the ratio of an output to an input (The figure above the function can be easily seen as representing the magnitude of the error transfer function, and not just the error magnitude for an input of fixed, 1 radian, value). The function in the next sub section instead -the jitter tolerance function- is not a transfer function. In fact even the aspect of causality (that in a transfer function is the fact that the input generates the output) is not present. The jitter tolerance function describes the values of input jitter that generate a fixed value of phase error.

In real applications the PLL circuit will not operate correctly any more when the phase difference between input and ouptput (i.e. when the magnitude of the error function) exceeds a certain value that can be called φ_c. Depending on the PLL design, it may slip abruptly by the phase amount of one clock cycle, or it may exhibit other irregularities of operation. It is good design practice to have the φ_c value, in all jitter conditions, to be larger than the error phase that the circuit is expected to tolerate. This situation of irregular operation is essentially encountered when the circuit non-linearities are reached. The next mathematical function, which corresponds also to a practical measurement condition for the circuit, is useful in describing the circuit behaviour when the boundaries of the non-linear operation are reached. This is the Jitter tolerance function, and is the subject of the following sub section.

Jitter tolerance function

In Telecom Networks it is established practice (see for instance the ITU-T Recommendations mentiones above) to specify, and to characetrise by the measurement of, the jitter that can be tolerated by the input ports of an equipment.
At any frequency of interest, a sinusoidal input jitter is added to the phase of an otherwise flawless incoming signal, and its amplitude is increased as much as the equipment can tolerate. Beyond that limit, the received data stream is not regenerated perfectly and errored bits or slips begin to appear in the regenerated stream.
The boundary of the area (in the plane of jitter frequencies and amplitudes) where correct operation is found is then called the curve of jitter tolerance of that equipment.

The errors can either be generated by sampling the received pulses with too large a phase error or by slips of a CDR clock internal to the equipment.

• Errored bits. If the CDR under test extracts the clock directly from the pulses of the received signal, and then uses it to regenerate the pulses received, then errored bits will give evidence of the tolerance limit. In this type of CDR the tolerance limit will be reached when the tracking error (the phase error) makes the sampling of the incoming signal excessively far (too early or too late) from the optimum point (the point of “maximum eye opening”).
• SLIPS. If the CDR under test extracts the clock from the clock of another CDR inside the same equipment (typically to dejitter it) then slips will give evidence of the tolerance limit.

In both cases, inside the CDR circuit (or circuits) involved, reaching the limit of tolerance corresponds to reaching a region of significant non-linearity inside one of the circuit blocks. It is useful to simulate (because this is often the case in reality, and also because this is very often a good simulation of the behaviour of the real circuit anyway) that the limit of the range of linearity is reached inside the phase comparator, abruptly, when the phase error reaches a value of +/- φ_t.

In mathematical terms either case above will be described by the phase (= the tracking) error exceeding a certain phase difference φ_t. Whichever occurs first for a smaller phase error is relevant for the value of the phase error best fit to give an accurate simulation, but the mathematical description (apart from an amplitude coefficient) is exactly the same. An elegant mathematical description of the 2nd order PLL in this condition can be easily obtained following in the abstract world of Laplace transform the steps described above. Let's consider the "transfer function" of phase error to input jitter, and let's restrict it to the condition ε(jω) = φ_t. Although it describes how the cause (the input jitter) corresponds to its effect (the phase error), it still nicely follows the way that the jitter tolerance is defined.

The function that gives the ratio of the input to the error when ε(jω) = 1 radian (that is the jitter tolerance function ) is:

The magnitude of this jitter tolerance function is :

The Bode magnitude plot (ω = 2πf) is given in the following figure:

This function can therefore be seen as the tolerance of our circuit (if φ_t = 1 radian) to an input sinusoidal jitter of the plotted magnitude. If another value of φ_t better simulates the circuit tolerance limit, the curve plotted still applies provided it is translated vertically by the amount . Image File history File links Size of this preview: 800 × 409 pixelsFull resolution (933 × 477 pixel, file size: 19 KB, MIME type: image/png) by Pierandrea Borgato Pierandrea Borgato 14:30, 17 August 2007 (UTC) Permission is granted to copy, distribute and/or modify this document under the terms of...

At low jitter frequencies there is very good tracking, even if the jitter has a large amplitude. The circuit has time to follow these large but slow variations. It takes an extremely large jitter amplitude to reach the limit of tolerance.

At very high jitter frequencies the circuit is unable to follow the jitter that varies too fast. The tolerance is in practice exactly the lateral eye opening (or the phase comparator range, whichever limit is reached first). In fact, the PLL is not able to track the jitter at all and the local clock stays unmoving with respect to it.

At intermediate jitter frequencies, just above f_n, the circuit is tricked by the jitter into overreaching while the jitter is coming back to its zero value. In the range of such intermediate frequencies, at and above f_n, the tolerance is correspondingly reduced below its asymptotic value, and especially so for low values of ζ.

The following table gives the values of the maximum tolerance reduction for different values of ζ.

Values of ζ between 1.0 and 1.5 are therefore an inevitable design choice. The designer shall pay attention to the fabrication tolerances of the CDR blocks (that may often be as large as ± 20 %) as well as to the dependence of them from operating conditions like the power supply variations or the density of transitions inside the incoming signal. Image File history File links No higher resolution available. ...

More on the jitter tolerance

In complex Telecom systems, the first CDR circuit met by the incoming signal (the first after the input stages of the receiver that perform amplification, equalisation and filtering) takes care of regenerating the clock with a given jitter tolerance. They are often implemented as Type 1 loops (“phase aligner”).

Another CDR circuit, somewhere else in the equipment and further down the signal path, takes care of controlling the jitter transfer function and filtering out enough of the noise (jitter) generated by the first CDR. The de-jittering CDRs are often implemented as Type 2 loops.

Without loss of generality, let's consider the scheme of the following figure.

The first CDR supplies the regenerated incoming pulse stream and its clock to the input of an elastic buffer, and supplies its clock also as input to the another CDR. The second CDR in turn, de-jitters the clock, and then uses it to get the data out of the elastic buffer. Image File history File links No higher resolution available. ...

• What is the combined Jitter transfer characteristic of the two CDRs?
  • The Jitter Tolerance of the cascade of the two CDRs is the locus of conditions that both can tolerate, and is therefore represented by the area below both curves (below the dark blue line). The Figure above represents the case of two similar CDRs, where the second is simply filtering the jitter more than the first. There is no advantage in having the first CDR more tolerant and better tracking than the second in such case.
  • The Jitter Transfer function of the cascade of the two CDRs is the product of the two transfer functions, as the figure indicates. In prectice, the jitter filtering is made by the second only.

An improvement in the combination of the two CDRs in cascade can be obtained if the second CDR (that must in any case be the one with tighter jitter filtering) has a different Jitter Tolerance characteristic for high jitter frequencies. The Figure below indicates how the combined characteristic looks, and also suggest one simple method of increasing the tolerance to high jitter frequencies in the second CDR.

The division by 4 (or more), inside CDR2, of both the clock to lock and of the local clock will be effective without drawbacks if the CDR1 is adequate to track the incoming signal. The division by 4 will remove from the CDR1 output the high jitter frequencies, and make the CDR2 insensitive to them at the same time. This should not cause problems, as long a the CDR2 is expected to filter out such high jitter frequencies. Image File history File links No higher resolution available. ...

It should be emphasized that the depth of the elastic buffer has no relevance in the jitter characteristics of the combination of the two CDRs, provided such depth is larger than the CDR2 tolerance at high jitter frequencies. In fact the buffer is represented in the above figures simply because it happens to be present in practical cases, but its presence is requested by system considerations other than the jitter characteristics, and is therefore always larger than required to match the jitter tolerance of CDR2.

CDR Phase comparators
- Examples and transfer functions

The Phase comparator or Phase detector is an essential part of ther CDR. The term phase comparator is preferred because this circuit block is expected to generate a signal that is proportional to the phase difference detected, and not simply to its sign. This article or section does not cite any references or sources. ...

Practical design values for ω_n and ζ of CDRs in Telecom Networks

*** Continuous transmission mode

*** Burst transmission mode

10 Gbit/s measurements of jitter parameters

The ITU-T specified jitter parameters are all measured in the frequency domain. They are related to the optical interface at the equipment level rather than to specific component characteristics. Although simple in definition, they can be difficult to evaluate at the component level.

Jitter tolerance

The jitter tolerance of receiving equipment is defined as the sinusoidal peak-to-peak modulation which causes a 1 dB optical penalty. When characterising a Clock and Data Recovery (CDR) component, white noise is added to the input signal. By varying the signal-to-noise ratio an input sensitivity curve of the CDR is obtained. It is then a simple matter to set the SNR to e.g. BER = 10-9 , add 2 dB (electrical) to the input signal and determine the peak-to-peak jitter amplitude that recovers the 10-9 BER. The data pattern used for the test is a 231 – 1 PRBS pattern for 10 Gbit/s.

Jitter transfer

The jitter transfer function is defined as the ratio of the output jitter relative to the jitter applied on the input, as a function of the input jitter frequency. The input sinusoidal jitter should conform to the amplitude versus frequency of the jitter tolerance mask (i.e. 1.5 UIpp up to 400 kHz and 0.15 UIpp above 4 MHz). The SNR level must be 2 dB (electrical) above the sensitivity limit and the pattern used is 231 – 1 PRBS. There are two distinct characteristics in jitter transfer:

• The jitter gain (or jitter peak) defined as the highest value found in the transfer characteristic, and
• The jitter transfer bandwidth.

{ In systems where several PLLs form the path from input to output, only the jitter gain is of importance to the Clock and Data Recovery circuit and to the Clock Generator of the output device. The overall jitter transfer bandwidth is controlled by a low bandwidth loop, typically using a VCXO. { In systems where the CDR is the only clock-generating element, the jitter transfer bandwidth together with jitter tolerance must conform to ITU-T specifications.

Jitter generation

Jitter generation is defined as the amount of jitter at an equipment output. In the case of transmission system components this parameter mostly relates to the characteristics of the Clock Generator(CG) of the output component. This CG can be a separate device, an integral part of a MUX device or, in the case of a one-PLL retiming device, the CDR’ clock output. The measurement requires an output clock or an ideal CDR that recovers the output data signal with a well-defined jitter transfer in the frequency range. The peak-to-peak value is obtained by integrating overall phase noise spectral components within the specified frequency range. A RMS value is obtained by the square root of the integrated squared phase noise amplitude spectrum.

More on the jitter generation

The source of jitter that probably most often troubles practical circuits, is the one coming from supply noise inside the CMos circuitry of the CDR itself. The internal supply rails inside an IC are affected by the high current transients generated inside output buffers, Clock trees and other large CMos stages inside the IC itself, even if such block are not part of the CDR proper. Those large current spikes will cause small ripple waves on the voltage supply lines. Other CMos stages, inside the receive paths and inside the CDR proper, will see –as a result of the supply ripples- their switching threshold ripple by exactly half the amount of the supply ripple. The rise and fall edges of the waveforms inside these CMos stages are not perfectly steep, but exhibit a certain non negligible slope. It is easy to see that a change of the threshold during the edge transition corresponds exactly to an earlier (or to a later) switching of the CMos stage: this time change, occurring almost at random at different transitions, will be nothing but a generated jitter. It can be minimised (and should be minimised) by careful design and layout of the supply scheme inside the IC.

See also

• Phase-locked loop
• 8B/10B encoding
• Eight-to-Fourteen Modulation
• Manchester code
• 64B/66B encoding
• B8ZS encoding
• HDB3 encoding
• Clock and data recovery
• Burst mode clock and data recovery