The Cray-2 is in the left foreground. To the right is the Cray-2's cooling tower, and in the left background is a Cray-1.

The Cray-2 was a vector supercomputer offered by Cray Research beginning in 1985. It was the fastest machine in the world when it was released, replaced Cray's own X-MP in that spot. The Cray-2 was bumped off of the top spot by the ETA-10G in 1990.

With the successful launch of the famed Cray-1, Cray immediately turned to the design of its successor. By 1979 he had become fed up with constant management interruptions in what was now a large company, and as had he had done in the past, decided to resign his management post and move to form a new lab. As with his original move to Chippewa Falls, Wisconsin from Control Data HQ in Minneapolis, MN, Cray management understood his needs and supported his move to a new lab in Boulder, Colorado. Working as an "independant consultant" he put together a team and started on a completely new design.

Cray had previously attacked the problem of increased speed with three simultaneous advances: more functional units to give the system higher parallelism, tighter packaging to decrease signal delays, and faster components to allow for a higher clock speed. For instance, the CDC 8600 packed four complete CDC 7600-like machines into a tiny 1 meter cylinder and cooled it with freon piping in order to allow its silicon-based transistors to run at a 8ns cycle time (125Mhz). The project failed because the cooling technology simply never worked right, and the complexity of the processors inside was so fiendish that there was almost always at least one minor construction problem that stopped them from working properly.

These problems had been addressed to some degree by the relentless improvements in integrated circuit design. IC's dramatically reduced the complexity problems through their automated construction technique; and they were so inexpensive that if one did fail to work properly, you simply threw it away and tried another one. The Cray-1 was their first design to use IC's, and although the clock speed was somewhat slower than the the 8600 (12.5ns vs 8ns), it nevertheless outran it by being able to pack considerably more logic into a reasonably sized box. On the downsize, IC's were not growing much denser in the 1970s, and in order to gain another 10-fold increase in performance (the baseline to design for) the machine would have to grow more complex. So once again they turned to a 8600-like solution, doubling the clock speed through increased density, adding more of these smaller processors into the basic system, and then attempting to deal with the problem of getting heat out of the machine.

Cray also felt that silicon technology had almost run its course; improvements on the Cray-1's 12.5ns cycle time were possible, but much more than doubling didn't seem easy. There was, however, the possibility of use gallium arsenide-based (GaAs) circuits instead, which offered at least 10 times the switching speed, and used less power to do it, thereby generating less heat as well. For some time in the late 1970's and early 80's it seemed a wholescale switch to GaAs was just around the corner, and a team from Cray worked with Rockwell International's semiconductor division to try to beat everyone to the punch. However the chips simply weren't ready for production, and the Cray-2 had to press ahead with existing silicon-based designs.

Cray-2 models soon settled on a design using large circuit boards absolutely packed with IC's. So packed, in fact, that they were almost impossible to solder together, and yet the density was still not nearly enough to reach their performance goals. Teams worked on the design for about two years before even Cray himself "gave up" and decided it would be best if they simply cancelled the project and fired everyone working on it. Les Davis, at Cray headquarters decided it would best be continued at low priority; after some minor personel movements the team continued on much as before.

Typical logic module, showing the increadibly tight packing. The "pogo" pins connecting the cards together are the gold-colored rods seen between the IC's. Courtesy Alan Kilian (http://bobodyne.com/web-docs/robots/cray2/)

Six months later Cray "got it". He called the main engineers together for a meeting and presented a new solution to the problem. Instead of making one larger circuit board, each "card" would instead consist of a stack of eight, connected together in the middle of the boards using pins sticking up from the surface (known as "pogos" or "z-pins"). The cards were packed right on top of each other, so the resulting stack was only about 3 inches high. With this sort of density there was no way any conventional cooling system would work; there was little room for air to flow between the IC's. Instead the system would be immersed in a tank of a new inert fluid from 3M, fluorinert. As the fluid heated it would rise to the top of the computer chassis where it was pumped to a separate cooling unit that used evaporative cooling.

Work on the new design started in earnest in 1982, several years after the original start date. The basic design used a single "foreground processor" to handle I/O tasks, connected with four separate Gb/s channels to a large main memory with a 128kB cache. On the other side of the processor were between four and sixteen "background processors", which did the actual math and vector calculations. In order to improve performance there was a set of eight 16-word (256 byte) prefetch buffers for feeding instructions into the background processors. In contrast to his earlier Control Data designs, the Cray-2 was somewhat "upside down"; earlier machines had used a number of foreground processors to deal with the very slow I/O devices of the era, ,and matched the performance of the processor to the maximum that the memory could handle. With the increased amount of memory bandwidth available the key to performance was to allow as many processors to run as quickly as possible against it. In order to make this work the data was supposed to be separated into different locations in memory, allowing the processors to access different parts of the data separately, and thus at the same time. The downside to this approach was that the cost of setting up the scatter/gather units that fed data into the processors was quite expensive. For small datasets or data that didn't lend itself to being spread out evenly the system would often be slower than a simpler architechture due to high latencies.

At this point the Cray X-MP was being developed under the direction of Steve Chen at Cray headquarters, and looked like it would give the Cray-2 a serious run for it's money. In order to address this internal threat, as well as a series of newer Japanese Cray-1-like machines, the Cray-2 memory system was dramatically improved, both in size as well as the number of "pipes" into the processors. When the machine was eventually delivered in 1985 the delays had been so long that much of its performance benefits were due to the fast memory, and the machine only really made sense to purchase for uses with huge data sets to process. The Cray-2 was predominantly developed for the American Departments of Defense and Energy. Uses tended to be for nuclear weapons research or oceanographic (sonar) development. However, the Cray-2 also found its way into civil agencies (such as NASA Ames Research Center), universities, and corporations worldwide. The Cray X-MP was used in most other roles where processing power was more important than memory, notably in cryptography and similar roles.

The Cray-2 would have been superseded by the Cray-3, but due to development problems; only one system was built and never paid for. The spiritual descendant of the Cray-2 is the Cray X1, offered by Cray Inc.

External links

Cray-2 (and -3) instruction set notes (http://klausler.com/cray2.txt)

Cray-2 module pictures (http://bobodyne.com/web-docs/robots/cray2/)