The DLX is a RISC processor architecture by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS with a simple 32-bit load/store architecture. Intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses. Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... A typical vision of a computer architecture as a series of abstraction layers: hardware, firmware, assembler, kernel, operating system and applications (see also Tanenbaum 79). ... John LeRoy Hennessy, the founder of MIPS Computer Systems Inc. ... David A. Patterson has been Professor of Computer Science at the University of California, Berkeley since 1977. ... A MIPS R4400 microprocessor made by Toshiba. ... Berkeley RISC was one of two seminal research projects into RISC-based microprocessor design taking place under ARPAs VLSI project. ... Representation of a university class, 1350s. ...

DLX instructions can be broken down into three types, R-type, I-type and J-type. R-type instructions are pure register instructions, with an operand and three registers contained in the 32-bit word. I-type instructions are similar, but use include a single register only, and use the 16-bits used to indicate the other two registers in the R-type to hold an immediate value. Finally J-type instructions are jumps, containing an operand and a 26-bit address.

Instructions are 6-bits in length, for a total of 64 possible basic instructions. 4-bits are needed to select one of sixteen registers. In the case of R-type instructions this means that only 18-bits of the 32-bit word are used, which allows the lower 6-bits to be used as "extended instructions". This allows the DLX to support more than 64 instructions, as long as those instructions work purely on registers. This is useful for things like FPU support. A floating point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. ...

The DLX, like the MIPS design, bases its performance on the use of an instruction pipeline. In the DLX design this is a fairly simple one, "classic" RISC in concept. The pipeline contains five stages: An instruction pipeline is a technique used in the design of microprocessors and other digital electronic devices to increase their performance. ...

• IF - Instruction Fetch unit

typically referred to as "the load unit" in modern terminology

• ID - Instruction Decode unit

this unit gets instruction from IF, and extracts opcode and operand from that instruction. It also retrieves register values if requested by the operation.

• EX - Execution unit

runs the instructions, typically referred to as the ALU in modern terminology

• MEM - Memory access unit

the MEM unit fetches data from main memory, under the control of the instructions from ID and EX.

• WB - WriteBack unit

typically referred to as "the store unit" in modern terminology.

In the original MIPS design one of the methods used to gain performance was to force all instructions to complete in one cycle, forcing the compiler to insert "noops" in cases where the instruction would definitely take longer, as in memory access for instance. The arithmetic logic unit/arithmetic-logic unit (ALU) of a computers CPU is a part of the execution unit, a core component of all CPUs. ...

In the DLX design a more modern approach to long instructions was used, using a data-forwarding system and reordering instructions. In this case the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they do complete. Externally it appears execution occurred linearly.

External links

• The DLX Processor
• DLX instructions
• WinDLX