EMMU is a custom MMU chip for the 130XE Atari 8-bit computer. It's used to access the extra 64kB of RAM present in the 130XE. MMU, short for Memory Management Unit, is a class of computer hardware components responsible for handling memory accesses requested by the CPU. Among the functions of such devices are the translation of virtual addresses to physical addresses (i. ... Atari built a series of 8-bit home computers based on the MOS Technology 6502 CPU, starting in 1979. ...
The user cannot directly manipulate the EMMU, but selects the various ROMS and memory banks via the memory-mapped hardware register known as PORTB (5401710 or D30116). Atari changed PORTB from a input port on the 400/800 machines to a output port on the XL/XE machines, leaving two joystick ports instead of four on the XL/XE machines.
By setting and clearing specific bits in PORTB, the user can access the extra 64kB of memory in 16kB increments. No synchronization is required as the OS handles the access.
The bits for PORTB are as follows:
Bit 0 - Controls OS ROM region. Disabling OS ROM enables RAM instead.
Bit 1 - Controls built-in BASIC. 0 for enable, 1 for disable.
Bit 2 - Controls LED #1 in the 1200XL. Controls bank-selection in the 130XE.
Bit 3 - Controls LED #2 in the 1200XL. Controls bank-selection in the 130XE.
Bit 4 - CPU bank enable bit for 130XE only.
Bit 5 - ANTIC bank enable bit for 130XE only.
Bit 6 - Unused.
Bit 7 - Controls the self test ROM region. Disabling self test enables RAM instead.
ATARI BASIC was a ROM resident BASIC interpreter for the Atari 8-bit family of 6502-based home computers. ...
EMMU wrapping logic 16 generates a main memory 9 address GJAD of the location of the segment descriptor by adding the displacement of the missing segment descriptor to a segment descriptor table physical base address and sends that address out over system bus 11 via 23 address signals GJAD and 23 drivers 11-2.
EMMU 3 is placed in a stall mode for the time it takes EMMU 3 to send the address information to main memory 9 and system bus 11 and to receive the two words from main memory 9 over system bus 11.
EMMU 3 firmware signals DCDG00- and DCDG02- are applied to negative NOR gates 20-6 and 20-12 respectively and are active during normal read/write operations.
Feeds |
Contact