The Efficeon processor is Transmeta's second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip (Code Morphing Software, aka CMS). Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint. Transmeta NASDAQ: TMTA develops computing technologies with a focus on reducing power consumption in electronic devices. ... A very long instruction word or VLIW CPU architectures implement a form of instruction level parallelism. ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... It has been suggested that some sections of this article be split into a new article entitled instruction set architecture. ... Crusoe is a family of x86-compatible microprocessors from Transmeta. ... In computer architecture, 128-bit integers, memory addresses, or other data units are those that are at most 128 bits wide. ...

Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. NX bit support is available starting with CMS version 6.0.4. Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The Pentium 4 is a seventh-generation x86 architecture microprocessor produced by Intel and was the companys first all-new CPU design since the Pentium Pro of 1995. ... Advanced Micro Devices, Inc. ... The AMD Opteron (codenamed SledgeHammer during development) was the first of AMDs eighth-generation x86 processors based on the K8 or Hammer core, and the first processor to implement the AMD64 (formerly x86-64) instruction set architecture. ... This article or section does not adequately cite its references or sources. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (aka code) or for storage of data, a feature normally only found in Harvard architecture processors. ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... In computing, Physical Address Extension (PAE) refers to a feature of x86 processors that allows for up to 64 gigabytes of physical memory to be used in 32-bit systems, given appropriate operating system support. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (aka code) or for storage of data, a feature normally only found in Harvard architecture processors. ...

Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors. Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... Introduced in March 2003, the Pentium M is an x86 architecture microprocessor designed and manufactured by Intel. ...

Efficeon comes in two package types: a 783 and a 592 ball grid array. Its power consumption is moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively cooled. Look up package in Wiktionary, the free dictionary. ... For the Bulgarian Go Association, see Bulgarian Go Association. ...

Two generations of this chip were produced. The first generation (TM8600) was manufactured using a TSMC 0.13 micrometre process and productized at speeds up to 1.1 GHz. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90 nm process and productized at speeds ranging from 1 GHz to 1.7 GHz). Taiwan Semiconductor Manufacturing Company, Limited (Traditional Chinese: 台灣積體電路製造股份有限公司, abbrev. ... A gigahertz is a billion hertz or a thousand megahertz, a measure of frequency. ... For the district in Saga, Japan, see Fujitsu, Saga. ...

Internally, the Efficeon has 2 arithmetic logic units, 2 load/store/add units, 2 execute units, 2 floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. This VLIW Processor can execute a 256-VLIW word per cycle, which is called a molecule and therefore has room and capability to execute 8 32-bit commands (called atoms) per cycle. The arithmetic logic unit/arithmetic-logic unit (ALU) of a computers CPU is a part of the execution unit, a core component of all CPUs. ... This article or section is in need of attention from an expert on the subject. ... MMX is a SIMD instruction set designed by Intel, introduced in 1997 in their Pentium MMX microprocessors. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE2, Streaming Single Instruction, Multiple Data Extensions 2, is one of the IA-32 SIMD instruction sets, first introduced by Intel with the initial version of the Pentium 4 in 2001. ... In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ...

The Efficeon has 128 k instruction + 64 k data level 1 cache and a 1Mb level 2 cache on the chip. Look up cache in Wiktionary, the free dictionary. ...

Additionally the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32Mb) for its translation cache of dynamically translated x86 instructions.

Products

Sharp Actius MP30
Microsoft FlexGo Computer

External links

• Transmeta Microprocessor Technology