EDA has rapidly increased in importance with the continuous scaling of semiconductor technology. (See: Moore's Law.) EDA companies clients are primarily semiconductor companies that design chips using EDA software. But also physical manufacturers (fabs), largest of which are TSMC, IBM, Intel.
EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing of the chips from design to mask generation.
Design and Architecture: design the chip's schematics, output in Verilog, VHDL, Spice and other formats.
Simulation: simulate circuit's work and detect any shortcomings
Place-n-Route, PR: placement of circuit elements on the chip layout, route all wires.
Physical Verification, PV: checking if design is physically manufacturable and resulting chips will not have any functioning preventing physical defects and meat original specifications
Design Rules Checking, DRC: checks number of rules of geometric and connectivity nature specified by manufacturer
Layout Versus Schematic, LVS: -- checks if designed chip layout matches schematics from specification
Mask Data Preparation, MDP -- generation of actual lithographymask used to physically manufacture the chip
Resolution Enhancement Techniques, RET: methods of increasing of quality of final mask
Optical Proximity Correction, OPC: up-front compensation for diffraction and interference effects occurring later when chip is manufactured using this mask
Mask Generation: generation of flat mask image from hierarchical design
Electronicdesign automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits.
Design closure is the process of converging to a design that satisfies all constraints simultaneously.
Design Automation software was developed in the 70s, in academia and within large companies, but it was not until the early 1980s that software to help with the design portion of the process became commercially available.
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