Itanium 2 Central processing unit
Itanium 2 processor
Produced:	From mid 2002 to present
Manufacturer:	Intel
CPU Speeds:	200 MHz to 1.4 GHz
FSB Speeds:	200 MHz to 533 MHz
Instruction Set:	IA-64
Cores: McKinley Madison Hondo Deerfield

Itanium 2 logo

The Itanium 2 is an IA-64 64-bit microprocessor developed jointly by Hewlett-Packard (HP) and Intel, and introduced on July 8, 2002. The first Itanium 2 processor (code-named McKinley) was substantially more powerful than the original Itanium, Intel's first IA-64 product. Several generations of Itanium 2 processors have followed, most recently a dual-core version (code-named Montecito) which, according to Intel, provides roughly 3.5 times the performance of the single-core Itanium 2 processors. [1] CPU redirects here. ... Image File history File links Dc_proc_lg. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... CPU redirects here. ... A megahertz (MHz) is one million (106) hertz, a measure of frequency. ... A gigahertz is a billion hertz or a thousand megahertz, a measure of frequency. ... In computers, the front side bus (FSB) is a term for the physical bi-directional data bus that carries all electronic signal information between the central processing unit (CPU) and other devices within the system such as random access memory (RAM), the system BIOS, AGP video cards, PCI expansion cards... A megahertz (MHz) is one million (106) hertz, a measure of frequency. ... A megahertz (MHz) is one million (106) hertz, a measure of frequency. ... An instruction set, or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any). ... In computing, IA-64 (or ia64, short for Intel Architecture-64) is a 64-bit processor architecture developed in cooperation by Intel and Hewlett-Packard, implemented by processors such as Itanium and Itanium 2. ... Image File history File links Logo_Itanium2Inside_100_3. ... In computing, IA-64 (or ia64, short for Intel Architecture-64) is a 64-bit processor architecture developed in cooperation by Intel and Hewlett-Packard, implemented by processors such as Itanium and Itanium 2. ... A microprocessor (sometimes abbreviated µP) is a digital electronic component with transistors on a single semiconductor integrated circuit (IC). ... The Hewlett-Packard Company (NYSE: HPQ), commonly known as HP, is a very large, global company headquartered in Palo Alto, California, United States. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... July 8 is the 189th day of the year (190th in leap years) in the Gregorian Calendar, with 176 days remaining. ... For album titles with the same name, see 2002 (album). ... Itanium 2 logo Old Itanium logo The Itanium is an IA-64 microprocessor developed jointly by Hewlett-Packard and Intel. ... In computing, IA-64 (or ia64, short for Intel Architecture-64) is a 64-bit processor architecture developed in cooperation by Intel and Hewlett-Packard, implemented by processors such as Itanium and Itanium 2. ... A dual-core CPU combines two independent processors and their respective caches and cache controllers onto a single silicon chip, or integrated circuit. ... Montecito is the code-name of a major release of Intels Itanium 2 Processor Family (IPF), which implements the IA-64 instruction set architecture on a dual-core processor. ...

Computing capabilities of Itanium

Floating-Point Performance

Floating-point performance is a function of both the ability to perform floating-point operations in parallel and the cycle time necessary for the processor to execute these operations. On the Itanium this number is increased by functional units which can perform two operations in a single pass. The Itanium is configured with two floating-point functional units known as floating-point multiply add calculations (FMACs), which can multiply two values and add that result to a third value. (Such operations are at the heart of many technical calculations.) Thus, an Itanium running at 800MHz can produce four floating-point results a cycle for a peak 64-bit performance rating of 3.2 billion floating-point operations per second (GFLOPS). The Itanium architecture also includes two single-precision (32-bit) FMACs that are tuned for 3D graphics performance which can each perform an additional four floating-point operations per cycle for a 6.4GFLOPS single-precision rating on an 800MHz processor. It is important to note that these performance numbers will automatically increase with each step-up of clock rates in the Itanium processor family. In addition, the Itanium architecture is designed to allow future versions of the processor to be configured with additional FMACs. The above analysis presents a best-case scenario in which the functional units are always busy. Although computer processors can maintain peak performance for only brief periods, Intel has incorporated a number of features in the Itanium architecture that help to maximize sustained performance. These include: In computing, FLOPS (or flops) is an acronym meaning Floating Point Operations Per Second. ... Explicitly Parallel Instruction Computing (EPIC) is a computing paradigm that began to be researched in the 1990s. ... In synchronous digital electronics, such as most computers, a clock signal is a signal used to coordinate the actions of two or more circuits. ...

• Pipelined functional units

Arithmetic operations generally require more than one machine cycle to complete. A pipelining scheme is used to allow the FMACs to produce results each cycle. The arithmetic operations are broken into a set of independent steps, each requiring one machine cycle to complete. The FMACs perform arithmetic operations in an assembly-line fashion, with each step accepting data from the previous step and sending results to the next step. Thus, after the pipeline is full, a result is produced each cycle.

• Dual-function arithmetic units

A secondary benefit of the dual function FMAC strategy is that the processor is able to use both functional units even when the distribution of adds and multiplies is biased toward one operation. For example, if a section of code performs only additions, both FMACs can be employed on the task. In contrast, a system with separate addition and multiplication functional units would use the adder but would have to leave the multiply unit idle.

• Large register sets

Intel designed the Itanium processor to support 128 integer, 128 floating point, 8 branch and 64 predicate registers (for comparison, IA-32 processors support 8 registers and other RISC processors support 32 registers). The use of these registers allows more database data and intermediate calculations to be stored in on-chip registers and reduces the repetitive load/store of intermediate data values. The more data that is directly available to the FMACs, the less likely a functional unit will stall due to lack of data. In addition, the large register sets provide a buffer for the memory system to move data in and out of memory. These capabilities combine to greatly improve the overall response time of an application’s database manipulation request. In computer architecture, a processor register is a small amount of very fast computer memory used to speed the execution of computer programs by providing quick access to commonly used values—typically, the values being in the midst of a calculation at a given point in time. ... In computing, a buffer is a region of memory used to temporarily hold output or input data, comparable to buffers in telecommunication. ...

• Internal parallelism

The Itanium can issue up to six instructions per cycles in a fixed set of combinations of four integer arithmetic/ logical operations, two load/store operations, two floating-point operations, and three branch operations. The advantage of double-precision or 64-bit operations over single-precision or 32-bit operations is that the former allow larger sets of calculations to be performed before accumulated round-off errors begin to affect the accuracy of the final results. Because 64-bit systems are able to produce 64-bit results in a single cycle, as opposed to two cycles for 32-bit systems, the speed of operations on 64-bit data types (such as doubles) is greatly increased. Multiple operations not only keeps as much of the processor working as possible but also allows for the pre-fetching of data from memory into registers and cache memory, thus minimizing processor stalls due to data unavailability. The processor also enables a load-double pair instruction to feed the processor with a balance of a memory operation per floating-point operation. In computing, double precision is a computer numbering format that occupies two storage locations in computer memory at address and address+1. ... This article is about the computer term. ... A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond. ...

• Compiler support for parallelism

The IA-64 architecture was designed to allow for closer coordination between the processor and compilers which generate the machine instructions for the processor. Three instructions are bundled along with a template field where the compiler can provide “hints” to the hardware on the interactions between the instructions. These hints are used by the processor to schedule instructions in real time and for pre-fetching of data for future operations. A diagram of the operation of a typical multi-language, multi-target compiler. ... Machine code or machine language is a system of instructions and data directly understandable by a computers central processing unit. ...

Memory Performance

Memory performance is measured in terms of both latency (i.e., how many cycles it takes to get data from memory to the processor) and bandwidth (i.e., how many bytes of data can be moved in a cycle). Many current systems attempt to solve the problems of latency and insufficient bandwidth through memory hierarchies, which include various levels of cache memory between main memory and the processor. Although this solution is effective, it is costly in terms of memory involved. The terms storage (U.K.) or memory (U.S.) refer to the parts of a digital computer that retain physical state (data) for some interval of time, possibly even after electrical power to the computer is turned off. ... In computing, memory latency is the time between initiating a request for a byte or word in memory until it is retrieved. ... Memory bandwidth is the amount of data per second that can be read from or stored into a semiconductor memory by a processor. ...

The Itanium 2 can read or write bytes of data to and from memory during every bus cycle; thus, for a 133MHz bus, the memory bandwidth is 2.1GBps. The 460GX chipset, which supports the Itanium processor, also has the ability to write an additional 2.1GBps from I/O to memory, for a total of 4.2GBps memory bandwidth. The Itanium processor uses a 4MB L3 (level 3) cache for quick access to large data structures such as texture maps for digital content applications. The L3 cache communicates with the 96KB L2 cache and the register file, moving data at 12.6GBps (16 bytes per 800MHz system clock) and with a 24-cycle latency for floating-point numbers.

The L2 cache feeds data directly into the floating-point registers at a rate of 32 bytes of data per clock tick and with a 9 clock latency. Although the L1 cache is by-passed by floating-point data, it is worth noting that it is divided into a 16KB instruction cache — L1I — and a 16KB integer data cache — L1D. Both caches operate on 2 clock latency to provide localized access to integer instructions and data, which is faster than retrieving the data from memory.

Because 64-bit systems have larger address spaces and are thus capable of having more memory — up to 1.8TB on the Itanium (the 460GX enables 64GB of physical memory; other original equipment manufacturer OEM systems can enable larger memory) — Itanium systems with sufficient RAM can load more of the program directly into memory, reducing the amount of time needed for read/write operations on the hard disk, which are ordinarily the most time-consuming operations for a computer (reading and writing data from a disk takes about 10 times longer than the same operation on memory). OEM is an acronym for either of the following: Original Equipment Manufacturer Office of Emergency Management. ... Look up RAM, Ram, ram in Wiktionary, the free dictionary. ... Typical hard drives of the mid-1990s. ...

Support for Large Data Sets

The requirements to operate on larger data sets generate in turn requirements for computer systems to provide larger real and virtual memories. A computer system’s addressable memory is usually determined by the size of its integer or address registers. 32-bit architectures can directly address 4GB of either real or virtual memory. Beyond this limit, some form of memory segmentation must be employed. 64-bit architectures can in theory address 2⁶⁴ bytes (16 exbibytes, or 10¹⁹ bytes) of data. As of November 2006, the machine with the largest amount of memory (arguably) in one address space is Red Storm with 8 petabytes of memory, so the 64-bit architecture should support even the largest machines for at least a decade without having to resort to some form of segmentation. An exbibyte (a contraction of exa binary byte) is a unit of information or computer storage, abbreviated EiB. 1 exbibyte = 260 bytes = 1,152,921,504,606,846,976 bytes = 1,024 pebibytes The exbibyte is closely related to the exabyte, which can either be a synonym for exbibyte, or... Red Storm is a computer architecture designed for the ASCI Thors Hammer supercomputer at Sandia National Laboratory and built by Cray, Inc as the XT3. ...

Programming model

One of the major advantages of 64-bit architectures is that because they allow larger amounts of both real and virtual memory, applications developers can design programs without having to divide the code into memory-sized segments. Such segmentation still exists, although it is less common today when nearly all servers have at least a gigabyte of memory available, and it requires developers to create code for managing the memory segments, hampering the program's performance. It has been suggested that this article be split into multiple articles. ...

Architectural Features and Attributes

The IA-64 architecture is based on a derivative of VLIW, dubbed Explicitly Parallel Instruction Computing (EPIC). It is theoretically capable of performing roughly 8 times more work per clock cycle than a non-superscalar CISC or RISC architecture due to its Parallel Computing Microarchitecture. However, performance is heavily dependent on software compilers and their ability to generate code which efficiently uses the available execution units of the processor. The Itanium 2 has seen heavy use in compute-bound supercomputers, and large corporate database servers, where parallelism and compile-time optimizations are most effective. A very long instruction word or VLIW CPU architectures implement a form of instruction level parallelism. ... Explicitly Parallel Instruction Computing (EPIC) is a computing paradigm that began to be researched in the 1990s. ... Processor board of a CRAY T3e parallel computer with four superscalar Alpha processors A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a single processor. ... A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... A supercomputer is a computer that leads the world in terms of processing capacity, particularly speed of calculation, at the time of its introduction. ... Parallelism may refer to: Parallelism (philosophy) - in the philosophy of mind a theistic, dualist solution to the mind-body problem Parallelism in computing Parallelism in grammar or in rhetoric This is a disambiguation page: a list of articles associated with the same title. ...

All Itanium 2 processors to date share a common cache hierarchy. They have 16 KiB of Level 1 instruction cache and 16 KiB of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256 KiB. The Level 3 cache is also unified and varies in size from 1.5 MiB to 24 MiB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU. The latest Itanium processor, however, features a split L2 cache, adding a dedicated 1MiB L2 cache for instructions and thereby effectively growing the original 256 KiB L2 cache, which becomes a dedicated data cache.

The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double pumped bus capable of 6.4 GB/s — more than three times the bandwidth of the original Itanium bus, known as the Merced bus. In 2004, Intel released processors with a 266 MHz bus, increasing bandwidth to 8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHz bus were released. In computing, a double pumped computer bus transfers data on both the rising and falling edges of the clock signal, effectively doubling the data transmission rate without having to deal with the additional problems of timing skew that increasing the number of data lines would introduce. ...

Most systems sold by enterprise server vendors that contain 4 or more processor sockets use proprietary Non-Uniform Memory Access (NUMA) architectures that supersede the more limited front side bus of 1 and 2 CPU socket servers. Non-Uniform Memory Access or Non-Uniform Memory Architecture (NUMA) is a computer memory design used in multiprocessors, where the memory access time depends on the memory location relative to a processor. ...

Itanium's major competitors include Sun Microsystems' UltraSPARC T1, IBM's Power5, AMD's Opteron, and Intel's own Xeon servers. In general, Itanium competes against Sun IBM systems, and Opterons for running enterprise-class workloads on large, multi-processor servers in the back-end of corporate datacenters. It competes against Opteron and Xeon-based servers in smaller configurations and in cluster configurations. Sun Microsystems, Inc. ... Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ... Big Blue redirects here. ... POWER5 dual-MCM POWER5 quad-MCM POWER5 is a microprocessor developed by IBM. It is an improved variant of the highly successful POWER4. ... Advanced Micro Devices, Inc. ... AMDs Opteron It should be possible to replace this fair use image with a free one. ... Xeon logo as of 2006. ...

Supercomputers

The best position ever acheived by an Itanium 2 based system in the TOP500 ranking of the fastest supercomputers was acheived in June 2004 when Thunder at LLNL entered the list at #2 with an Rmax of 19.94 Teraflops. It was second only to the Japanese Earth Simulator. It had 4096 1.4Ghz Itanium 2 processors and was connected by a Quadrics QsNet II interconnect. As of November 2006, this system has slipped to position #19. The website TOP500 (www. ... A supercomputer is a computer that leads the world in terms of processing capacity, particularly speed of calculation, at the time of its introduction. ... ESC cabinets The Earth Simulator (ES) was the fastest supercomputer in the world from 2002 to 2004, located at the Earth Simulator Center (ESC) in Kanazawa-ku (ward), Yokohama-shi, Japan. ... This is an article about the computing company, for use in mathematics, see quadric. ...

In the November 2006 list there were three other Itanium 2 based systems in the top 20:

• #7 Tera-10, Commissariat a l'Energie Atomique (CEA), France. Machine: Bull SMP Cluster, NovaScale 5160. CPU: 8,704 Itanium 2 (1.6 GHz). Connection: Quadrics QsNet II. Main Memory: 26112 GB. Rmax: 42.9 Teraflops.

• #8 Columbia, NASA/Ames Research Center/NAS. Machine: SGI Altix 3700. CPU: 10,160 Itanium 2 (1.5 GHz). Connection: SGI NUMAlink / Voltaire Infiniband. Rmax: 51.87 Teraflops.

• #18 HLRB II, Leibniz Rechenzentrum, Baveria, Germany. Machine: SGI Altix 4700. CPU: 4,096 Itanium 2 (1.6 GHz). Connection: SGI NUMAlink. Rmax: 24.36 Teraflops

The peak number of Itanium-based machines on the list occured on the November 2004 list at 16.8%. In November 2006 the number is 7.0% QsNetII is the latest generation of Quadrics Interconnect family products. ... NUMAlink is a high-speed low-latency switched fabric computer bus used as a computer cluster processor interconnection system. ... InfiniBand is a switched fabric communications link primarily used in high-performance computing. ...

Itanium 2 processor versions

McKinley

McKinley was the first version of the Itanium 2 processor, manufactured in an 180 nm process. It was released at speeds of 900 MHz and 1 GHz, with cache sizes of 1.5 MiB and 3 MiB. It added hardware support for the branchlong instruction of the IA-64 instruction set. IA-32 performance, while improved, was still much slower than that of contemporanious x86 processors; McKinley's x86 performance was similar to that of a Pentium II at 2/3 the clock speed. It has been suggested that this article or section be merged with X86 assembly language. ... Pentium II – front view The Pentium II is an x86 architecture microprocessor by Intel, introduced on May 7, 1997. ...

Madison

Madison was initially introduced on June 30, 2003. It was initially available in three versions: 1.3 GHz with 3 MiB of cache, 1.4 GHz with 4 MiB of cache and 1.5 GHz with 6 MiB of cache. Manufactured in a 130 nm process, it had a die size of 374 mm². Its power envelope remained unchanged from McKinley at 130 watts. On September 8, 2003, a 1.4 GHz version with 1.5 MiB of cache was released. 1.4 GHz and 1.6 GHz versions with 3 MiB of cache were launched on April 13, 2004. November 8, 2004 saw the release of the first processor in the Madison 9M series, at 1.6 GHz with 9 MiB of cache. On July 18, 2005, more variations of the Madison 9M were introduced, including 1.67 GHz models with a 333 MHz FSB and either 6 MiB or 9 MiB of cache. On introduction, the latter part set a record SPECfp result of 2,801 in a Hitachi, Ltd. Computing blade. June 30 is the 181st day of the year (182nd in leap years) in the Gregorian Calendar, with 184 days remaining. ... 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ... The watt (symbol: W) is the SI derived unit of power, equal to one joule per second. ... September 8 is the 251st day of the year (252nd in leap years). ... 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ... April 13 is the 103rd day of the year in the Gregorian calendar (104th in leap years). ... 2004 (MMIV) was a leap year starting on Thursday of the Gregorian calendar. ... November 8 is the 312th day of the year (313th in leap years) in the Gregorian Calendar, with 53 days remaining. ... 2004 (MMIV) was a leap year starting on Thursday of the Gregorian calendar. ... July 18 is the 199th day (200th in leap years) of the year in the Gregorian Calendar, with 166 days remaining. ... 2005 (MMV) was a common year starting on Saturday of the Gregorian calendar. ... The Standards Performance Evaluation Corporation (SPEC) is a non-profit organization that aims to produce fair, impartial and meaningful benchmarks for computers. ... It has been suggested that Hitachi Works be merged into this article or section. ... In computing marketing-speak, the term blade designates a standardised module which one can plug in to a computer system - after the manner of a changeable blade in a kitchen appliance. ...

In January 2005 OpenVMS was added to the line up of Operating Systems able to run on these processors. OpenVMS[1] (Open Virtual Memory System or just VMS) is the name of a high-end computer server operating system that runs on the VAX[2] and Alpha[3] family of computers developed by Digital Equipment Corporation of Maynard, Massachusetts (DIGITAL was then purchased by Compaq, and is now owned...

Hondo

Hondo was announced as the HP mx2 dual-processor module on February 18, 2003 and started shipping in early 2004. It consists of two Madison cores with 32 MiB of L4 cache and fits in the same space as a normal Itanium 2 CPU. It is only available from HP. Currently the cores run at 1.1 GHz with 4 MiB L3 cache each. February 18 is the 49th day of the year in the Gregorian Calendar. ... 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ...

OpenVMS for Itanium is able to use the MX2 variant. OpenVMS[1] (Open Virtual Memory System or just VMS) is the name of a high-end computer server operating system that runs on the VAX[2] and Alpha[3] family of computers developed by Digital Equipment Corporation of Maynard, Massachusetts (DIGITAL was then purchased by Compaq, and is now owned...

Deerfield

Deerfield was released on September 8, 2003. With 1.5 MiB of cache, running at 1 GHz, this was the first low voltage Itanium processor. Its 62 watt power envelope made it more suited for blade and 1U servers. September 8 is the 251st day of the year (252nd in leap years). ... 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ...

Fanwood

The Fanwood core debuted on November 8, 2004. Versions include a 1.6 GHz edition with 3 MiB of L3 cache with either 200 MHz or 266 MHz FSB and a low voltage 1.3 GHz version with 3 MiB L3 cache at 200 MHz. November 8 is the 312th day of the year (313th in leap years) in the Gregorian Calendar, with 53 days remaining. ... 2004 (MMIV) was a leap year starting on Thursday of the Gregorian calendar. ... In computers, the front side bus (FSB) is a term for the physical bi-directional data bus that carries all electronic signal information between the central processing unit (CPU) and other devices within the system such as random access memory (RAM), the system BIOS, AGP video cards, PCI expansion cards...

Montecito

Main article: Montecito (processor)

The Dual-Core Intel® Itanium® 2 processor 9000 series (code-named Montecito) was released on July 18, 2006. Montecito is the first Itanium processor to have two cores per die. It was originally planned to feature advanced power and thermal management improvements. However, the originally planned Foxton dynamic clock speed feature was removed due to unspecified engineering issues (it is under consideration by Intel for inclusion in future Itanium 2 processor versions). Despite the elimination of this feature, Intel reports that Montecito doubles the performance of its single-core predecessor, while reducing power consumption by approximately 20 percent. [2] It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization. Manufactured in a 90nm process, Montecito debuted with speeds between 1.4 GHz for a low-power configuration and 1.6 GHz / 12 + 12 MiB L3 at the high end. The FSB runs at 400 MHz and 533 MHz. Montecito is the code-name of a major release of Intels Itanium 2 Processor Family (IPF), which implements the IA-64 instruction set architecture on a dual-core processor. ... In computers, the front side bus (FSB) is a term for the physical bi-directional data bus that carries all electronic signal information between the central processing unit (CPU) and other devices within the system such as random access memory (RAM), the system BIOS, AGP video cards, PCI expansion cards...

Upcoming revisions

This article contains information about a scheduled or expected future product. It may contain preliminary or speculative information, and may not reflect the final version of the product.

The future of the Itanium family apparently lies in multi-core chips, as the available information about coming generations, such as Montvale and Tukwila shows. (Those are internal code names; the final products will most likely also bear the Itanium brand, possibly as Itanium 3 or perhaps just Itanium 2.). Wikipedia does not have an article with this exact name. ...

Montvale

Main article: Montvale (processor)

Montvale is expected to be a revision of Montecito bringing higher clock speeds, larger caches, and a faster FSB. Montvale is the code-name of a future release of Intels Itanium Processor Family (IPF), which implements the IA-64 instruction set architecture. ...

Tukwila

Main article: Tukwila (processor)

Tukwila, the first 65 nanometer design, is due in 2008. Tukwila will consist of 4 cores, with each core being multithreaded. It is going to feature a new bus called Common System Interface and an on-die memory controller. Ultimately, CSI is intended to provide socket compatibility with Xeon processors; however, as of October 2005, the CSI roadmap for Xeon processors has been delayed until at least 2009. Tukwila is the code-name for a future generation of Intels Itanium processor family following Itanium 2 and Montecito. ... The 65 nanometer (65 nm) process is (as of 2006) the most advanced lithographic node for volume semiconductor manufacturing, however it will soon be eclipsed when 45 nanometer lithography becomes commercially viable. ... It has been proposed below that Common System Interface be renamed and moved to Common System Interconnect. ...

Poulson

Main article: Poulson (processor)

Few details are known, other than the existence of the codename. Poulson is the code-name for a future generation of Intels Itanium 2 processor family. ...

External links

• Intel Itanium 2 technical specifications
• Some undocumented Itanium 2 microarchitectural information