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Encyclopedia > Launch Vehicle Digital Computer

The Saturn Launch Vehicle Digital Computer (LVDC) was one of the major components of the Instrument Unit fitted to the S-IVB stage of the Saturn V and Saturn IB rockets. Its primary role was to provide an autopilot for the Saturn from launch to orbit insertion, but it also supported pre- and post-launch checkout of the Saturn hardware. Diagram of Saturn V Instrument Unit. ... The S-IVB (sometimes S4b) was built by the Douglas Aircraft Company and served as the third stage on the Saturn V and second stage on the Saturn IB. It had one J-2 engine. ... This article is about the rocket. ... The Saturn IB was an uprated version of the Saturn I, which was the first manned launch vehicle that was not directly derived from an ICBM (though its tanks were derived from the Jupiter and Redstone tanks, and its first stage engines were Navaho derived). ...

Contents

Hardware

By today's standards the LVDC was extremely slow, with a 2.048 MHz clock cycle, add operations taking 82 microseconds (vs a fraction of a nanosecond on a Pentium 4) and memory holding a maximum of 32,768 28-bit words in memory modules of 4096 words each, each equivalent to less than sixteen kilobytes. However, for the 1960s it was a sophisticated system, and easily capable of flying a two-thousand ton rocket into a hundred mile high orbit. New Intel Pentium 4 with Hyper Threading logo The Pentium 4 was a seventh-generation x86 architecture microprocessor produced by Intel and was the companys first all-new CPU design since the Pentium Pro of 1995. ...


The computer processed 26-bit data (25 bits of magnitude and one sign bit), with two extra parity bits for error detection, and instructions were 13 bits in size with one parity bit. This meant that two instructions could fit in one data word, making the limited memory size less constricting for software. Main memory was random access magnetic core, with ultrasonic delay lines for temporary storage. A parity bit is a binary digit that indicates whether the number of bits with value of one in a given set of bits is even or odd. ... A 16×16 cm area core memory plane of 128×128 bits, i. ... Mercury memory of UNIVAC I (1951) Delay line memory was a form of computer memory used on some of the earliest digital computers, such as the EDSAC and UNIVAC I. The basic concept of the delay line originated with World War II radar research, specifically to reduce clutter from reflections...


For reliability the LVDC used triple-redundant logic and a voting system. The computer included three identical logic systems each split into a seven stage pipeline, and at each stage in the pipeline a voting system would take a majority vote on the results, with the most popular result being passed on to the next stage in all pipelines. This meant that for any of the seven stages one module in any one one of the three pipelines could fail, and the LVDC would still produce the correct results. The result was an estimated reliability of 99.6% over 250 hours of operation, which was far more than the few hours required for an Apollo mission.


With four memory modules, giving a total capacity of 16384 words, the computer weighed 72.5 pounds (approx 35 kilograms), was 29.5"x12.5"x10.5" in size (74x32x27 cm) and consumed 137 watts of power, the latter at least beating a modern PC.


Software

LVDC instruction words were split into a 4-bit operand field and a 9-bit address field. Unfortunately this left it with sixteen possible operand values when there were eighteen different instructions: consequently, three of the instructions used the same operand value, and used two bits of the address value to determine which instruction was executed.


The eighteen possible LVDC instructions were:

Instruction Function
HOP Transfer execution to a different part of the program. Unlike a modern 'jump' instruction the operand address did not actually specify the address to jump to, but pointed to a 26-bit 'HOP constant' which specified the address.
MPY Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. This instruction took four instruction cycles to complete, but didn't stall program execution, so other instructions could execute before it finished.
SUB Subtract the contents of the memory location specified in the operand address from the accumulator register.
DIV Divide the contents of the memory location specified in the operand address into the accumulator. This instruction took eight instruction cycles to complete, but didn't stall program execution.
TNZ Tranfers instruction execution to the operand address specified if the accumulator contents are not zero.
MPH Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. Unlike MPY, this instruction does halt execution until the multiplication is complete.
AND Logically AND the contents of the accumulator with the contents of the memory location specified in the operand address.
ADD Add the contents of the memory location specified in the operand address to the accumulator register.
TRA Transfer execution to the memory location specified in the operand address.
XOR Logically XOR the contents of the accumulator with the contents of the memory location specified in the operand address.
PIO Process input or output: communicate with external hardware.
STO Store the contents of the accumulator register in the memory location specified in the operand address.
TMI Transfer execution to the operand address specified if the accumulator contents are negative.
RSU Contents of the accumulator are subtracted from the contents of the memory location specified in the operand address, and the result left in the accumulator.
SHF Contents of accumulator are shifted by up to two bits, based on a value in the operand address. This instruction can also clear the accumulator if the operand address bits are zero.
CDS Change data sector.
EXM Transfer execution to one of eight addresses dependent on the operand address, which also specifies modifications to the operand address of the next instruction before it is executed.

Unfortunately, unlike the Apollo Guidance Computer, the software which ran on the LVDC seems to have vanished. While the hardware would be fairly simple to emulate, the only remaining copies of the software are probably in the core memory of the Instrument Unit LVDCs of the remaining Saturn V rockets on display at NASA sites. The Apollo Guidance Computer (AGC) was the first recognizably modern embedded system, used in real-time by astronaut pilots to collect and provide flight information, and to automatically control all of the navigational functions of the Apollo spacecraft. ... Diagram of Saturn V Instrument Unit. ... This article is about the rocket. ...


Interrupts

The LVDC could also respond to a number of interrupts triggered by external events.


For a Saturn IB these interrupts were:

LVDC Data Word Bit Function
1 Internal to LVDC
2 Spare
3 Simultaneous Memory Error
4 Command Decoder Interrupt
5 Guidance Reference Release
6 Manual Initiation of S-IVB Engine Cutoff
7 S-IB Outboard Engines Cutoff
8 S-IVB Engine Out
9 RCA-110A Interrupt
10 S-IB Low Fuel Level Sensors Dry
11 RCA-110A Interrupt

For a Saturn V these interrupts were:

LVDC Data Word Bit Function
1 Minor Loop Interrupt
2 Switch Selector Interrupt
3 Computer Interface Unit Interrupt
4 Temporary Loss Of Control
5 Command Receiver Interrupt
6 Guidance Reference Release
7 S-II Propellant Depletion/Engine Cutoff
8 S-IC Propellant Depletion/Engine Cutoff
9 S-IVB Engine Out
10 Program Recycle (RCA-110A Interrupt)
11 S-IC Inboard Engine Out
12 Command LVDA/RCA-110A Interrupt

References

External links


  Results from FactBites:
 
Apollo Guidance Computer - Wikipedia, the free encyclopedia (4017 words)
The Apollo Guidance Computer (AGC) was the first recognizably modern embedded system, used in real-time by astronaut pilots to collect and provide flight information, and to automatically control all of the navigational functions of the Apollo spacecraft.
The computer's RAM was magnetic core memory (4K words) and ROM was implemented as core rope memory (32K words).
These errors automatically aborted the computer's current task, but the frequency of radar data ensured that the abort signals were being sent at too great a rate for the CPU to cope [5].
  More results at FactBites »


 

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