This article or section contains information about scheduled or expected future product(s). It may contain information of a speculative nature and the content may change dramatically as the product release approaches and more information becomes available.

Montecito is the code-name of the next major release of Intel's Itanium Processor Family (IPF), which implements the IA-64 instruction set architecture. It is not known what the official marketing name will be, but the production samples seen at the 2005 Intel Developer Forum were still labelled as Itanium 2s. Wikipedia does not have an article with this exact name. ... Intel Corporation (NASDAQ: INTC) (HKSE: 4335) (founded 1968) is a U.S.-based multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... Itanium brand logo The Intel Itanium processor. ... In computing, IA-64 (Intel Architecture-64) is a 64-bit processor architecture developed in cooperation by Intel and Hewlett-Packard, implemented by processors such as Itanium and Itanium 2. ... Itanium 2 brand logo The Itanium 2 is the successor of the first Itanium processor and is an IA-64 architecture microprocessor. ...

Expected Features and Attributes

Die photo

Die description

Micrograph

Die power

Core power breakdown

• Two cores per die
• 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, database-like workloads should improve by 15-35%.
• a total of 4 threads per die
• separate 16 KB Instruction L1 and 16 KB Data L1 cache per core
• separate 1 MB Instruction L2 and 256 KB Data L2 cache per core, improved hierarchy
• 12 MB L3 cache per core, 24 MB L3 per die
• 1.72 billion transistors per die, which is added up from:
  • core logic — 57M, or 28.5M per core
  • core caches — 106.5M
  • 24 MB L3 cache — 1550M
  • bus logic & I/O — 6.7M
• Die size is 27.72 mm x 21.5 mm, or 596 mm²
• 90 nanometer design
• Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count and higher clock speeds; 100 W has been suggested. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistor were used, while high-speed, thus high-leakage ones where it was necessary.
• Demand Base Switching — power saving feature. Dynamically reduces processor power consumption based on demand or load. Works in conjunction with the OS. Could reduce server power consumption for typical CPU utilization.
• Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This is Pellston technology.
• Virtualization technology allowing multiple OS instances per chip. This is Silvervale technology.
• Improved, higher bandwidth front side bus (FSB), with three times the capacity of the existing bus design. What is not known yet is whether it meant to be at device level (per die) or at system level (per node, with 4 dies). System throughput per node will be at least 21 GB/s.
• Will also be available with legacy FSB for upgrading existing system designs
• FSB speed of 267MHz (double pumped) is expected for the initial release.

According to a French source, x86-secret.com, Montecito would have made its debut in Q405 with the following models, but these offerings may no longer be accurate after the announced delays in October 2005: Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ... Image File history File links File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to this old version. ...

• Itanium 2 9055 1.8(2.0) GHz / 24 MB L3
• Itanium 2 9040 1.6(1.8) GHz / 18 MB L3
• Itanium 2 9030 1.7(1.8) GHz / 8 MB L3
• Itanium 2 9020 1.4(1.6) GHz / 12 MB L3
• Itanium 2 9018 LV 1.2(1.4) GHz / 12 MB L3
• Itanium 2 9010 1.6(1.8) GHz / 6 MB L3

Foxton power management

The original design called for an advanced clock scaling technology for power management, known as Foxton. The clock rate is not fixed, but adjusted to a nominal power envelope. That means that clock and voltage are adjusted to keep the chips consumption within the envelope. Depending on the actual usage pattern the chip will be able to scale up or down, feeding the core with proper voltage. Under so called low activity workloads which generate less heat while being executed Montecito speeds up till it reaches the target power, and vica versa, extreme activity loads may cause the chip to reduce clock rate and core voltage. Additionally, the nominal power envelope can be adjusted from software. Low-activity workloads are rather integer-intensive computations, mostly commercial, database applications. They should be boosted by around a factor of 10% compared to a "fixed clock" scenario. High activity workloads are rather floating point-intensive computations, like scientific and R&D simulations. Nominal clock speeds of chips might be based on power drained by these intensive computations. It was said earlier that Foxton's clock scaling can be disabled if required.

However, due to problems with Foxton in the current stepping of the Montecito chip, it seems that a Q106 release is likely, with the fastest launch device running at 1.6 (1.8) GHz. Higher speeds (e.g. a 2 (2.2) GHz version) will likely arrive later in 2006. This delay may be a result of the validation process of such a highly complex high-end MPU. Unofficial insider sources confirmed, that Montecio will reach 2.2 GHz with Foxton. The maximum Montecito's design is validated for is 2.5 GHz, but it's more likely that it will actually top out around 2.2 GHz.

On October 25, 2005 it was officially announced by Intel that Montecito would be delayed until "the middle of next year", and that it will no longer ship with the Foxton power-management technology, and its front-side bus will run at 267MHz instead of the 333MHz speed originally scheduled for the design.[1]

Successors

Montvale

In contrast to earlier speculations, there will be no 65 nm shrink, but the codename Montvale will cover a Montecito on-steroids, released one year later, tail end of 2006. Earlier data suggested that Montvale's clock speed would have likely hit 2.5-2.6 GHz, sitting on a 400 MHz FSB. As of today, Montvale might reach only 2 GHz, or something, and considering Montecito's delay, it may slip as well. Map highlighting Montvales location within Bergen County. ...

It is also very likely, that like Montecito, Montvale will also bring an update of the compiler technology, with significant improvement in performance characteristics to IPF.

Tukwila

Montvale's successor is Tukwila, the first 65 nm design, due in 2008. Consisting of at least 4 cores, which will likely be microachitecturally the same as Montecito's ones, it should fit into the so called Common Serial Interconnect, dubbed CSI, a cross-platform with Xeons. A major advancement is not expected till Poulson, which is very little known about this time. Tukwila is the code-name for a future generation of Intels Itanium processor family following Itanium 2 and Montecito. ...

External links

• Real World Technologies: Sizing up the Super Heavyweights, an analysis and comparison of Montecito and POWER5 with performance estimates, by Paul DeMone

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