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Encyclopedia > POWER4
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The POWER4 chip is a computer processor that implements the IBM POWER and 64-bit PowerPC instruction set architectures. Released in 2001, the POWER4 chip is based on the previous POWER3 chip design. The POWER4 chip is a multicore chip, including two PowerPC cores. 2005 : January - February - March - April - May - June - July - August - September - October - November - December- → Deaths in June June 27: Shelby Foote June 27: John T. Walton June 26: Richard Whiteley June 25: John Fiedler June 25: Chet Helms June 24: Paul Winchell June 21: Jaime Cardinal Sin June 20: Jack Kilby... To meet Wikipedias quality standards, this article or section may require cleanup. ... In computing, a 64-bit component is one in which data are processed or stored in 64-bit units (words). ... PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. ... An instruction set, or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any). ... 2001: A Space Odyssey. ... Released in 1998: 15 million transistors per chip The first 64-bit symmetric multiprocessor (SMP), POWER3 is completely compatible with the original POWER instruction set -- and compatible with the PowerPC instruction set as well. ... A multicore processor is a chip with more than one processing units (cores). ...

Contents


Functional Layout

The functional unit of the POWER4™ consists of two 64-bit implementations of the PowerPC AS Architecture. An L2 unified cache which is divided into three equal parts each having it own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) which connects each L2 controller to either the (data cache/instruction cache) in either of the two processors. A NonCacheable (NC) Unit is devoted to each processor which is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology. An L3 cache controler, and the directory of the L3 (but the actual memory is off-chip). A GX bus controller which controlles I/O device communications, and two 4-byte wide GX buses one for Incoming and the other for Outgoing. A Fabric Controller which is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4™ chips {4-way, 8-way, 16-way, 32-way} and POWER4™ MCM’s. Trace-and-Debug (used for First Failure Data Capture). A Built In Self Test function (BIST). Performance Monitoring Unit (PMU). Power-On Reset (POR).


Execution Unit

The POWER4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using 8 independent execution units. The 8 are: 2 floating-point units(FP1-2), 2 load-store units(LD1-2), 2 fixed-point units(FX1-2), 1 branch unit(BR), and 1 conditional-register unit(CR).

  • Branch Prediction
  • Instruction Fetch
  • Decode, Crack and Group Formation
  • Group Dispatch and Instruction Issue
  • Load/Store Unit Operation
    • Load Hit Store
    • Store Hit Load
    • Load Hit Load
  • Instruction Execution Pipeline

Multi-Chip Configuration

IBM POWER4 MCM
Enlarge
IBM POWER4 MCM

Not only did the POWER4 become the first microprocessor to incorporate Dual-cores in a single die, but it also concurrently became the first to implement a Multi-Chip-Module(MCM) which contains four POWER4 Microprocessors in a single package. This work is copyrighted. ... This work is copyrighted. ...


Parametrics

POWER4 18nm@CMOS 8S3 SOI
Clock GHz >1.3
Power 115 W 1.5 V @ 1.1 GHz
Transistors 174 million
Gate L 90 nm
Gate oxide 2.3 nm
Metal-layer pitch thickness
M1 500 nm 310 nm
M2 630 nm 310 nm
M3-M5 630 nm 420 nm
M6(MQ) 1260 nm 920 nm
M7(LM) 1260 nm 920 nm
Dielectric ~4.2
Vdd 1.6 V

See also

POWER is a RISC CPU architecture designed by IBM. The name stands for Performance Optimization With Enhanced RISC. The POWER series microprocessors are used as the main CPU in many of IBMs servers, minicomputers, workstations, and supercomputers. ... PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. ...

References


  Results from FactBites:
 
IBM POWER4 Processor Review (2285 words)
The POWER4 consists of 2 identical processor cores which implement PowerPC AS instruction set, the die measures about 400 mm2, it's based on the 0.18 micron copper SOI IBM CMOS 8S2 technology with 7 metallization layers, works at 1.1 and 1.3 GHz, and is the fastest microprocessor for today.
The L1 cache is capable of delivering to the front part of the pipeline up to 8 instructions per clock according to the address given by the IFAR register the contents of which is determined by the branch prediction unit.
The POWER4 has a hardware prefetch unit which loads data into the L1 cache from the whole memory hierarchy, and there are instructions which allow controlling this process on a software level.
The circuit and physical design of the POWER4 microprocessor (11661 words)
The POWER4 chips were fabricated in the state-of-the-art IBM 0.18-µm CMOS 8S3 SOI (silicon-on-insulator) technology with seven levels of copper wiring [4].
At the start of the POWER4 microprocessor design, a tool suite and methodology were put together by picking the best elements of established IBM microprocessor design methodologies, such as POWER3, S/390* G4, and PowerPC 615 [6, 7], and combining them with new ideas specific to this design.
For a total POWER4 chip power of ~115 W and a maximum transient power change of ~25 W, it was necessary to embed 250 nF of decoupling capacitance into critical areas of the chip.
  More results at FactBites »


 

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