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Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar CPUs. SMT permits multiple independent threads of execution to better utilize the resources provided by modern processor architectures. Image File history File links Merge-arrow. ... Multithreading computers have hardware support to efficiently execute multiple threads. ... Simple superscalar pipeline. ... “CPU” redirects here. ... For the form of code consisting entirely of subroutine calls, see Threaded code. ... CPU design is the hardware design of a central processing unit. ...

Details

Multithreading is similar in concept to preemptive multitasking but is implemented at the thread level of execution in modern super-scalar processors. Pre-emptive multitasking is a form of multitasking in which processes are not allowed to take an indefinitely long time to complete execution in the CPU. Each process, in turn, is granted a portion of CPU time (usually called a time slice, on the order of milliseconds). ... For the form of code consisting entirely of subroutine calls, see Threaded code. ...

Simultaneous multithreading (SMT) is one of the two main implementations of multithreading, the other form being temporal multithreading. In temporal multithreading, only one thread of instructions can execute in any given pipeline stage at a time. In simultaneous multithreading, instructions from more than one thread can be executing in any given pipeline stage at a time. This is done without great changes to the basic processor architecture: the main additions needed are the ability to fetch instructions from multiple threads in a cycle, and a larger register file to hold data from multiple threads. The number of concurrent threads can be decided by the chip designers, but practical restrictions on chip complexity have limited the number to two for most SMT implementations. Temporal multithreading is one of the two main forms of multithreading that can be implemented on computer processor hardware, the other form being Simultaneous multithreading. ...

Since the technique is really an efficiency solution, and there is inevitable increased conflict on shared resources, measuring or agreeing on the effectiveness of the solution can be difficult. Some researchers have shown that the extra threads can be used to proactively seed a shared resource like a cache, to improve the performance of another single thread, and claim this shows that SMT is not just an efficiency solution. Others use SMT to provide redundant computation, for some level of error detection and recovery.

But, in most current cases, SMT is about hiding memory latency, efficiency and increased throughput of computations per amount of hardware used.

Taxonomy

In processor design, there are two ways to increase on-chip parallelism with less resource requirement: one is superscalar technique which tries to increase Instruction Level Parallelism (ILP), the other is multithreading approach exploiting Thread Level Parallelism (TLP). Simple superscalar pipeline. ... Many programming languages, operating systems, and other software development environments support what are called threads of execution. ...

Superscalar means executing multiple instructions at the same time while chip-level multithreading (CMT) executes instructions from multiple threads within one processor chip at the same time. There are many ways to support more than one thread within a chip, namely:

• Interleaved multithreading: Interleaved issue of multiple instructions from different threads. It can be further divided into fine-grain multithreading or coarse-grain multithreading depending on the frequency of interleaved issues. Fine-grain multithreading issues instructions for different threads after every cycle, while coarse-grain multithreading only switches to issue instructions from another thread when the current executing thread causes some long latency events (like page fault etc.). Coarse-grain multithreading is more common for less context switch between threads. For example, Intel's Montecito processor uses coarse-grain multithreading, while Sun's UltraSPARC T1 uses fine-grain multithreading.
• Simultaneous multithreading (SMT): Issue multiple instructions from multiple threads in one cycle.
• Chip-level multiprocessing (CMP or multicore): integrates two or more superscalar processors into one chip, each executes threads independently
• Any combination of multithreaded/SMT/CMP

The key factor to distinguish them is to look at how many instructions the processor can issue in one cycle and how many threads from which the instructions come. For example, Sun Microsystems' UltraSPARC T1 (known as "Niagara" until its November 14, 2005 release) is a multicore processor combined with fine-grain multithreading technique instead of simultaneous multithreading because each core can only issue one instruction at a time. Montecito is the code-name of a major release of Intels Itanium 2 Processor Family (IPF), which implements the IA-64 instruction set architecture on a dual-core processor. ... Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ... Diagram of an Intel Core 2 dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache. ...

Historical implementations

While multithreading CPUs have been around since the 1950s, Simultaneous Multithreading was first researched by IBM in 1968. The first major commercial CPU developed with SMT was the DEC 21464 (EV8). This chip was developed by DEC in coordination with Dean Tullsen of the University of California, San Diego, and Susan Eggers and Hank Levy of the University of Washington. The processor was never released, since the Alpha line of processors was discontinued shortly before HP acquired Compaq (formerly DEC). Dean Tullsen's work was also used to create the Intel Pentium 4 Processor. DEC Alpha AXP 21064 Microprocessor die photo Package for DEC Alpha AXP 21064 Microprocessor Alpha AXP 21064 bare die mounted on a business card with some statistics The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp... DEC, dec or Dec may refer to: December - a month of the year in the Gregorian Calendar Department of Environment and Conservation Digital Equipment Corporation - a computer and technology company, now part of HP Declination - a term from astronomy Diethylcarbamazine - a drug commonly used to treat infections by filarial parasites... HP may refer to: Handley Page Aircraft Company Harry Potter, a series of fantasy novels by British writer J. K. Rowling Hello! Project (H!P), a Japanese pop recording project Hewlett-Packard, a computer and computer peripheral company High Point, North Carolina High potency, a term used in biology, pharmacology... Compaq Computer Corporation is an American personal computer company founded in 1982, and now a brand name of Hewlett-Packard. ... DEC, dec or Dec may refer to: December - a month of the year in the Gregorian Calendar Department of Environment and Conservation Digital Equipment Corporation - a computer and technology company, now part of HP Declination - a term from astronomy Diethylcarbamazine - a drug commonly used to treat infections by filarial parasites...

Modern commercial implementations

The Intel Pentium 4 was the first modern desktop processor to implement simultaneous multithreading, starting from the 2.8GHz model released in 2002, and since introduced into a number of their processors. Intel calls the functionality Hyper-Threading Technology (HTT), and provides a basic two-thread SMT engine. Intel claims up to a 30% speed improvement compared against an otherwise identical, non-SMT Pentium 4. The performance improvement seen is very application dependent, and some programs actually slow down slightly when HTT is turned on due to increased contention for resources such as bandwidth, caches, TLBs, re-order buffer entries, etc. Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The Pentium 4[1] brand refers to Intels mainstream desktop and mobile single-core CPUs (introduced on November 20, 2000[2]) with the seventh-generation NetBurst architecture, which was the companys first all-new design since the Intel P6 of the Pentium Pro branded CPUs of 1995. ... Hyper-Threading (HTT = Hyper Threading Technology) is Intels trademark for their implementation of the simultaneous multithreading technology on the Pentium 4 microarchitecture. ... A Translation Lookaside Buffer (TLB) is a cache in a CPU that is used to improve the speed of virtual address translation. ...

The latest MIPS architecture designs include an SMT system known as "MIPS MT". MIPS MT provides for both heavyweight virtual processing elements and lighter-weight hardware microthreads. RMI, a Cupertino-based startup, is the first MIPS vendor to provide a processor SOC based on 8 cores, each of which runs 4 threads. The threads can be run in fine-grain mode where a different thread can be executed each cycle. The threads can also be assigned priorities. A MIPS R4400 microprocessor made by Toshiba. ...

The IBM POWER5, announced in May 2004, comes as either a dual core DCM, or quad-core or 8-core MCM, with each core including a two-thread SMT engine. IBM's implementation is more sophisticated than the previous ones, because it can assign a different priority to the various threads, is more fine-grained, and the SMT engine can be turned on and off dynamically, to better execute those workloads where an SMT processor would not increase performance. This is IBM's second implementation of generally available hardware multithreading. For other uses, see IBM (disambiguation) and Big Blue. ... POWER5 dual-MCM POWER5 quad-MCM POWER5 is a microprocessor developed by IBM. It is an improved variant of the highly successful POWER4. ...

Although many people reported that Sun Microsystems' UltraSPARC T1 (known as "Niagara" until its 14 November 2005 release) and the upcoming processor codenamed "Rock" (to be launched ~2007) are implementations of SPARC focused almost entirely on exploiting SMT and CMP techniques, Niagara is not actually using SMT. Sun refers to these combined approaches as "CMT", and the overall concept as "Throughput Computing". The Niagara chip uses fine-grained multithreading. Unlike SMT, where instructions from multiple threads share the issue window each cycle, the processor uses a round robin policy to issue instructions from the next active thread each cycle. This makes it more similar to a Barrel processor. Sun Microsystems, Inc. ... Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ... A code name or cryptonym is a word or name used clandestinely to refer to another name or word. ... Rock is planned multithreading, multicore microprocessor currently in development at Sun Microsystems. ... Sun UltraSPARC II Microprocessor Sun UltraSPARC T1 (Niagara 8 Core) SPARC (Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems. ... Diagram of an Intel Core 2 dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache. ... A barrel processor is a CPU that switches between threads of execution on every cycle. ...

See also

• Thread (computer science), what is executed
• Symmetric multiprocessing uses multiple processors

For the form of code consisting entirely of subroutine calls, see Threaded code. ... Symmetric multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. ...

References

• LE Shar and ES Davidson, "A Multiminiprocessor System Implemented through Pipelining", Computer Feb 1974
• D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," In 22nd Annual International Symposium on Computer Architecture, June, 1995
• D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm, "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor," In 23rd Annual International Symposium on Computer Architecture, May, 1996

External links

• SMT news articles and academic papers
• SMT research at the University of Washington
• Timeline of multithreading technologies