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In computer architecture, a systolic array is a pipe network arrangement of data processing units (DPUs (see figure, for instance, with 32 bit wide DPUs). DPUs are similar to central processing units (CPU)s, but do not have a program counter, since operation is transport-triggered, i.e., by the arrival of a data object (also used in transport triggered architectures), in an array (often rectangular) where data flows across the array between neighbours, usually with different data flowing in different directions. The data streams entering and leaving the ports of the array are generated by auto-sequencing memory units (ASMs). Each ASM includes a data counter. In Embedded Systems a data stream may also be input from and/or output to an external source. Image File history File links Broom_icon. ... A typical vision of a computer architecture as a series of abstraction layers: hardware, firmware, assembler, kernel, operating system and applications (see also Tanenbaum 79). ... To meet Wikipedias quality standards, this article or section may require cleanup. ... DPU can stand for: in computing: Data Path Unit in quality management: Defects per Unit. ... Die of an Intel 80486DX2 microprocessor (actual size: 12×6. ... CPU can stand for: in computing: Central processing unit in journalism: Commonwealth Press Union in law enforcement: Crime prevention unit in software: Critical patch update, a type of software patch distributed by Oracle Corporation in Macleans College is often known as Ash Lim. ... The program counter (also called the instruction pointer in some computers) is a register in a computer processor which indicates where the computer is in its instruction sequence. ... Transport triggered architecture (TTA) is an application-specific instruction set processor (ASIP) architecture template that allows easy customization of microprocessor designs. ... This article or section does not cite its references or sources. ... Look up Data stream in Wiktionary, the free dictionary. ... An Auto-sequencing memory (ASM) block is a RAM memory unit including an address generator with a data counter (a data pointer) used as a data address register for implementation of a data stream. ... Data counters are used instead of a program counter by the basic model (non von Neumann) of Reconfigurable Computing systems. ... A router, an example of an embedded system. ...

The systolic array paradigm, data-stream-driven by data counters, is the counterpart of the von Neumann paradigm, instruction-stream-driven by a program counter (see von Neumann or von Neumann architecture). Because a systolic array includes multiple data counters, it supports data parallelism. The name derives from analogy with the regular pumping of blood by the heart. Image File history File links Size of this preview: 568 × 516 pixelsFull resolution (568 × 516 pixel, file size: 29 KB, MIME type: image/jpeg) Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1. ... Image File history File links Size of this preview: 568 × 516 pixelsFull resolution (568 × 516 pixel, file size: 29 KB, MIME type: image/jpeg) Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1. ... A separate article covers Saint John Neumann, the American priest. ... Design of the Von Neumann architecture For the robotic architecture also named after Von Neumann, see Von Neumann machine The von Neumann architecture is a computer design model that uses a single storage structure to hold both instructions and data. ... Data Parallelism is a form of parallelization of computer code. ... Systole can mean the following: Systole (medicine) is a term describing the contraction of the heart. ...

H. T. Kung and Charles E. Leiserson published the first paper describing systolic arrays in 1978; however, the first machine known to have used the technique was the Colossus Mark II in 1944. H. T. Kung is a computer scientist. ... Charles E. Leiserson is a computer scientist, specializing in the theory of parallel computing and distributed computing, and particularly practical applications thereof; as part of this effort, he developed the Cilk multithreaded language. ... 1978 (MCMLXXVIII) was a common year starting on Sunday. ... A Colossus Mark II computer. ...

Each processor at each step takes in data from one or more neighbours (e.g. North and West), processes it and, in the next step, outputs results in the opposite direction (South and East).

An example of a systolic algorithm might be matrix multiplication. One matrix is fed in a row at a time from the top of the array and is passed down the array, the other matrix is fed in a column at a time from the left hand side of the array and passes from left to right. Dummy values are then passed in until each processor has seen one whole row and one whole column. At this point, the result of the multiplication is stored in the array and can now be output a row or a column at a time, flowing down or across the array. In mathematics, computing, linguistics, and related disciplines, an algorithm is a finite set of well-defined instructions for accomplishing some task which, given an initial state, will terminate in a defined end-state. ... This article gives an overview of the various ways to perform matrix multiplication. ... For the square matrix section, see square matrix. ...

Systolic Arrays Systolic arrays are arrays of processors which are connected to a small number of nearest neighbours in a mesh-like topology. Processors perform a sequence of operations on data that flows between them. Generally the operations will be the same in each processor, with each processor performing an operation (or small number of operations) on a data item and them passing it on to its neighbour. Like SIMD machines, systolic arrays compute in "lock-step" with each processor undertaking alternate compute | communicate phases. One well-known systolic array is CMU's iWarp processor, which has been manufactured by Intel. An iWarp system has a linear array processors connected by data buses going in both directions.

An Example - Poynomial Evaluation Horner's rule for evaluating a polynomial is: y = ((((anx + an-1)*x + an-2)*x + an-3)*x .... a1)*x + a0

A linear systolic array in which the processors are arranged in pairs: one multiplies its input by x and passes the result to the right, the next adds aj and passes the result to the right:

See also

• SISAL
• KressArray - Reconfigurable version of Super systolic array

Binomial name Agave sisalana Perrine Sisal or sisal hemp is an agave Agave sisalana that yields a stiff fiber used in making rope. ... The introduction of this article does not provide enough context for readers unfamiliar with the subject. ...

External links

• Instruction Systolic Array (ISA)
• KressArray
• Generalization of the systolic array (Super systolic array)

This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL. The Free On-line Dictionary of Computing (FOLDOC) is an online, searchable encyclopedic dictionary of computing subjects. ... GNU logo (similar in appearance to a gnu) The GNU Free Documentation License (GNU FDL or simply GFDL) is a copyleft license for free content, designed by the Free Software Foundation (FSF) for the GNU project. ...