|
SPARC (Scalable Processor ARChitecture) is a RISC microprocessor architecture originally designed in 1985 by Sun Microsystems. SPARC is a registered trademark of SPARC International, Inc., an organisation established in 1989 to promote the SPARC and to provide conformance testing. SPARC International was intended to "open" the SPARC architecture to make a larger ecosystem for the design, and has been licensed to several manufacturers, including Texas Instruments, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary: there's a fully open source implementation called LEON which VHDL source code is available under LGPL.
Implementations of SPARC architecture were initially designed and used for workstations, and then used for larger SMP servers produced by Sun Microsystems and Fujitsu among others.
There have been several revisions of the architecture. Most recent ones are the version 8 and the version 9.
Features The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California, Berkeley. These original RISC designs were minimalist, including as few features or op-codes as possible and demanding that all operations complete in one cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.
The SPARC processor usually contains as many as 128 general purpose registers. At any point, only 32 of them are available - 8 are global registers and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for keeping values across function calls. The "Scalable" in SPARC comes from the fact that the SPARC specification allows up to 32 windows. So the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement minimum to reduce the context switching time. Other architectures that include similar register windows include Intel i960, IA-64, and AMD 29000.
Floating point registers. In version 8, the floating-point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. Version 9 added 16 more double precision registers, but these additional double precision registers can not be used as single precision registers.
Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.
History The architecture has gone through a few revisions and has gained multiply and divide functionality in version 8. The most substantial upgrade resulted in the version 9 which is a 64-bit SPARC specification.
Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, so as to be used as reference systems for SPEC CPU95 and CPU2000 benchmarks.
| SPARC microprocessor specifications | | Model | Frequency
[Mhz] | Architecture
Version | Year | Process
[µm] | Transistors
[millions] | Die size
[mm²] | IO Pins | Power
[W] | Voltage
[V] | Dcache
[k] | Icache
[k] | Scache
[k] | | microSPARC I | 50 | V8 | 1992 | 0.8 | 0.8 | 225 | 288 | 2.5 | 5 | 4 | 2 | none | | SuperSPARC I | 50-80 | V8 | 1992 | 0.8 | 3.1 | -- | -- | 14.3 | 5 | 16 | 20 | 1024 | | microSPARC II | 80-125 | V8 | 1992 | 0.5 | 2.3 | 233 | 321 | 5 | 3.3 | 8 | 16 | none | | SuperSPARC II | 75-85 | V8 | 1994 | 0.8 | 3.1 | 299 | -- | 16 | -- | 20 | 16 | 1024 | | UltraSPARC I | 140-200 | V9 | 1995 | 0.5 | 5.2 | 315 | 521 | 30 | 3.3 | 16 | 16 | 1024 | | UltraSPARC II | 250-400 | V9 | 1997 | 0.25 | 5.4 | 156 | 521 | 21 | 3.3 | 16 | 16 | 8192 | | UltraSPARC IIi | 270-480 | V9 | 1998 | 0.25 | 5.4 | 148 | 370 | 17.6 | 1.7 | 16 | 16 | 8192 | | UltraSPARC IIe | 400-500 | V9 | 2000 | 0.18 | 5.4 | -- | 370 | 13 | 1.7 | 16 | 16 | 8192 | | UltraSPARC III | 600-1200 | V9 | 2001 | 0.13 | 29 | 330 | 1368 | 53 | 1.6 | 64 | 32 | 8192 | | UltraSPARC IIIi | 1064-1280 | V9 | 2003 | 0.13 | 87.5 | 206 | 959 | 52 | 1.3 | 64 | 32 | 16384 | | UltraSPARC IV | 1050-1200 | V9 | 2004 | 0.13 | 66 | 356 | 1368 | 108 | 1.35 | 64 | 32 | 16384 |
External links | 
Feeds |
Contact