VHDL, or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. A VHSIC is a Very-High-Speed Integrated Circuit, a type of digital logic circuit. ... In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. ... An Altera Stratix II GX FPGA. A field-programmable gate array is a semiconductor device containing programmable logic components and programmable interconnects. ... This article does not cite any references or sources. ... PCB Layout Program Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. ... Digital circuits are electric circuits based on a number of discrete voltage levels. ...

History

VHDL was originally developed at the behest of the US Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex manuals which were subject to implementation-specific details. Motto: (Out Of Many, One) (traditional) In God We Trust (1956 to date) Anthem: The Star-Spangled Banner Capital Washington D.C. Largest city New York City None at federal level (English de facto) Government Federal constitutional republic  - President George Walker Bush (R)  - Vice President Dick Cheney (R) Independence from... The United States Department of Defense (DOD or DoD) is the federal department charged with coordinating and supervising all agencies and functions of the government relating directly to national security and the military. ... This article does not cite any references or sources. ...

The idea of being able to simulate this documentation was so obviously attractive that logic simulators were developed that could read the VHDL files. The next step was the development of logic synthesis tools that read the VHDL, and output a definition of the physical implementation of the circuit. Modern synthesis tools can extract RAM, counter, and arithmetic blocks out of the code, and implement them according to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest cost, highest power efficiency, highest speed, or other requirements. Logic simulation is the use of a computer program to simulate the operation of a digital circuit. ... Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL) or behavioral) is turned into a design implementation in terms of logic gates. ... Random access memory (usually known by its acronym, RAM) is a type of data storage used in computers. ... In general, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. ...

VHDL borrows heavily from the Ada (programming language) in both concepts (for example, the slice notation for indexing part of a one-dimensional array) and syntax. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly-typed and case insensitive. There are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor, in order to represent directly operations which are common in hardware. VHDL also allows arrays to be indexed in either direction (ascending or descending) because both conventions are used in hardware, whereas Ada (like most programming languages) provides ascending indexing only. The reason for the similarity between the two languages is that the Department of Defense required as much as possible of the syntax to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada. Ada is a structured, statically typed imperative computer programming language designed by a team led by Jean Ichbiah of CII Honeywell Bull under contract to the United States Department of Defense during 1977–1983. ... In computing, strongly-typed, when applied to a programming language, is used to describe how the language handles datatypes. ... Text sometimes exhibits case sensitivity, that is, words can differ in meaning based on the differing use of uppercase and lowercase letters. ... The United States Department of Defense (DOD or DoD) is the federal department charged with coordinating and supervising all agencies and functions of the government relating directly to national security and the military. ...

The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide range of data types, including numerical (integer and real), logical (bit and boolean), character and time, plus arrays of bit called bit_vector and of character called string. The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ... The integers are commonly denoted by the above symbol. ... On computer science, a datatype (often simply type) is a name or label for a set of values and some operations which can be performed on that set of values. ... This article is about the unit of information. ... In abstract algebra, a Boolean algebra is an algebraic structure (a collection of elements and operations on them obeying defining axioms) that captures essential properties of both set operations and logic operations. ... A pocket watch, a device used to tell time Look up time in Wiktionary, the free dictionary. ... This article or section does not cite its references or sources. ... In computer programming and some branches of mathematics, strings are sequences of various simple objects. ...

A problem not solved by this edition, however, was "multi-valued logic", where a signal's drive strength (none, weak or strong) and unknown values are also considered. This required IEEE standard 1164, which defined the 9-value logic types: scalar std_ulogic and its vector version std_ulogic_vector. The IEEE Standard 1164 defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description. ...

The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to allow ISO-8859-1 printable characters, added the xnor operator, etc. The IEEE Standard 1076 defines the VHSIC Hardware Description Language or VHDL. It was originally developed by CLSI under contract F33615-83-C-1003 from the United States Airforce in 1983. ...

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and microwave circuit design extensions. Microwaves are electromagnetic waves with wavelengths longer than those of terahertz (THz) frequencies, but relatively short for radio waves. ...

In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to work on next update of the standard) approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of 'case' and 'generate' statements, incorporation of VHPI (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

Discussion

VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements. Verilog is a hardware description language (HDL) used to model electronic systems. ... In computing, strongly-typed, when applied to a programming language, is used to describe how the language handles datatypes. ... Flaming is the act of posting messages that are deliberately hostile and insulting, usually in the social context of a discussion board (usually on the Internet). ... A transparent latch is an electronic data storage device with a data input (D), an enable input (E) and a data output (Q). ... In digital circuits, the flip-flop, latch, or bistable multivibrator is an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. ...

The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures. Design of the Von Neumann architecture For the robotic architecture also named after Von Neumann, see Von Neumann machine The von Neumann architecture is a computer design model that uses a single storage structure to hold both instructions and data. ...

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip. An Altera MAX 7000-series CPLD with 2500 gates. ... A field-programmable gate array or FPGA is a gate array that can be reprogrammed after it is manufactured, rather than having its programming fixed during the manufacturing — a programmable logic device. ...

Getting started

To start coding in VHDL, one needs a simulation tool, at the very least. While very few open source VHDL simulators exist today, most commercial vendors offer free, but often limited, versions of their software.

Furthermore, it is highly recommended to use a synthesis tool even when you do not plan to test your code on real hardware. The reason for this is that you can often see the graphical representation (i.e. gates) of your code after synthesis. Seeing what kind of hardware correspond to your code is a very important step in learning any HDL and becoming a good designer. Wikipedia does not yet have an article with this exact name. ...

As a side note, the graphical representation is sometimes available in two version: RTL (which is more generic) and technology-mapped gates (which is the RTL mapped to the cells that are available in the target hardware). In integrated circuit design, Register Transfer Level (RTL) description is a way of describing the operation of a synchronous digital circuit. ...

Today, almost all FPGA vendors offer trial versions of their complete toolchain free of cost. These tools are more than enough for the beginners to start with, and also sometimes include very valuable documents and tutorials. A field-programmable gate array or FPGA is a gate array that can be reprogrammed after it is manufactured, rather than having its programming fixed during the manufacturing — a programmable logic device. ...

• Limited to vendor's device-database

Code examples

In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and configurations.

A simple AND gate in VHDL would look something like this: A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. ...

 -- (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity name_of_entity is port ( IN1 : in std_logic; IN2 : in std_logic; OUT1: out std_logic); end entity name_of_entity; -- here comes the architecture architecture name_of_architecture of name_of_entity is -- Internal signals and components would be defined here begin OUT1 <= IN1 and IN2; end architecture name_of_architecture; 

While the example above may seem very verbose to HDL beginners, one should keep in mind that many parts are either optional or need to be written only once. In addition, use of elements such as the 'std_logic' type might at first seem an overkill. One could easily use the built-in 'bit' type and avoid the library import in the beginning. However, using this 9-valued logic (U,X,0,1,Z,W,H,L,-) instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

In the examples that follow, you will see that VHDL code can be written in a very compact form. However, the experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability.

Synthesizeable constructs and VHDL templates

Originally synthesizers, which would correspond to compilers in the HDL world, used a set of templates to identify the common hardware constructs in the HDL code (recall that VHDL is a hardware 'description' language, not a programming language). These templates can still be used today, although the HDL tools are far more sophisticated these days. Due to their usually one-to-one mapping to well known digital circuits, the templates are usually what an otherwise experienced hardware designer would use when entering the HDL world. But they are also useful for those who are completely new to digital design.

Some digital components have multiple templates, consider for instance the multiplexor example that follows:

MUX templates

The multiplexer, or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputs A and B, selector S and output X: Schematic of a 2-to-1 Multiplexer. ...

 -- template 1: X <= A when S = '1' else B; -- template 2: with S select X <= A when '1' else B; -- template 3: process(A,B,S) begin case S is when '1' => X <= A; when others => X <= B; end case; end process; -- template 4: process(A,B,S) begin if S = '1' then X <= A; else X <= B; end if; end process; 

The two last templates make use of what VHDL calls 'sequential' code. The sequential sections are always placed inside a process and have a slightly different syntax which may resemble more traditional programming languages.

Latch templates

A transparent latch is basically one bit of memory which is updated when an enable signal is raised: A transparent latch is an electronic data storage device with a data input (D), an enable input (E) and a data output (Q). ...

 -- latch template 1: Q <= D when Enable = '1' else Q; -- latch template 2: process(D,Enable) begin if Enable = '1' then Q <= D; end if; end process; 

A SR-latch uses a set and reset signal instead: In electronics, a latch is data storage device used to store information in asynchronous sequential logic systems. ...

 -- SR-latch template 1: Q <= '1' when S = '1' else '0' when R = '1' else Q; -- SR-latch template 2: process(S,R) begin if S = '1' then Q <= '1'; elsif R = '1' then Q <= '0'; end if; end process; -- This one is a RS-latch (i.e. reset dominates) process(S,R) begin if R = '1' then Q <= '0'; elsif S = '1' then Q <= '1'; end if; end process; 

D-type flip-flops

The D-type flip-flop samples an incoming signal at the rising or falling edge of a clock. The DFF is the basis for all synchronous logic. In digital circuits, the flip-flop, latch, or bistable multivibrator is an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. ...

 -- simplest DFF template (not recommended) Q <= D when rising_edge(CLK); -- recommended DFF template: process(CLK) begin -- use falling_edge(CLK) to sample at the falling edge instead if rising_edge(CLK) then Q <= D; end if; end process; -- alternative DFF template: process begin wait until rising_edge(CLK); Q <= D; end process; 

Some flip-flops also have Enable signals and asynchronous or synchronous Set and Reset signals:

 -- template for asynchronous reset with clock enable: process(CLK, RESET) begin if RESET = '1' then -- or '0' if RESET is active low... Q <= '0'; elsif rising_edge(CLK) then if Enable = '1' then -- or '0' if Enable is active low... Q <= D; end if; end if; end process; -- template for synchronous reset with clock enable: process(CLK) begin if rising_edge(CLK) then if RESET = '1' then Q <= '0'; elsif Enable = '1' then -- or '0' if Enable is active low... Q <= D; end if; end if; end process; 

A common beginner mistake is to have a set or reset input but not use it. For example, the following two snippets are not equal, the first one is a simple D-type flip-flop, while the second one is a DFF with a feedback MUX.

 -- simple D-type flip-flop process(CLK) begin if rising_edge(CLK) then Q <= D; end if; end process; -- BAD VHDL: this does NOT make the flip-flop a DFF without a reset!! process(CLK, RESET) begin if RESET = '1' then -- do nothing. Q is not set here... elsif rising_edge(CLK) then Q <= D; end if; end process; 

This is very similar to the 'transparent latch' mistake mentioned earlier.

The counter example

The following example is a counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type and VHDL generics. The generic are very close to templates in, for example, C++ or other traditional programming languages.

 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type entity counter_example is generic ( WIDTH : integer := 32); port ( CLK, RESET, LOAD : in std_logic; DATA : in unsigned(WIDTH-1 downto 0); Q : out unsigned(WIDTH-1 downto 0)); end entity counter_example; architecture counter_example_a of counter_example is signal cnt : unsigned(WIDTH-1 downto 0); begin Q <= cnt; process(RESET, CLK) begin if RESET = '1' then cnt <= (others => '0'); elsif rising_edge(CLK) then if LOAD = '1' then cnt <= DATA; else cnt <= cnt + 1; end if; end if; end process; end architecture counter_example_a; 

Fibonacci series

The following example is slightly more complex:

 -- Fib.vhd -- -- Fibonacci number sequence generator library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Fibonacci is port ( Reset : in std_logic; Clock : in std_logic; Number : out unsigned(31 downto 0) ); end entity Fibonacci; architecture Rcingham of Fibonacci is signal Previous : natural; signal Current : natural; signal Next_Fib : natural; begin Adder: Next_Fib <= Current + Previous; Registers: process (Clock, Reset) is begin if Reset = '1' then Previous <= 1; Current <= 1; elsif rising_edge(Clock) then Previous <= Current; Current <= Next_Fib; end if; end process Registers; Number <= to_unsigned(Previous, 32); end architecture Rcingham; 

When simulated, it generates the Fibonacci sequence successfully, until Next_Fib overflows the range of the natural type. When synthesized with an FPGA vendor's tools, an "Adder" module was implemented, as hoped for. Otherwise, the assignment statement would have to be replaced by a component instantiation to logic that implements that function. In mathematics, the Fibonacci numbers form a sequence defined recursively by: In words: you start with 0 and 1, and then produce the next Fibonacci number by adding the two previous Fibonacci numbers. ...

Simulation-only constructs

A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging. For example, the following code will generate a clock with the frequency of 50 MHz. It can, for example, be used to drive a clock input in a design during simulation. It is however a simulation-only construct and can not be implemented in hardware!

 process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process; 

The simulation-only constructs can be used to build complex waveforms in very short time. Such waveform can be used, for example, as test vectors for a complex design or as a prototype of some synthesizable logic that will be implemented in future.

 process begin wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop; -- wait until the output changes wait until RESULT'event; -- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0'; -- and so on... end process; 

References

See also

• Verilog
• SystemC
• Register transfer level
• Electronic design automation

Verilog is a hardware description language (HDL) used to model electronic systems. ... SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power during transaction-level modeling and behavioral modeling. ... In integrated circuit design, Register Transfer Level (RTL) description is a way of describing the operation of a synchronous digital circuit. ... PCB Layout Program Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. ...

External links

• The FAQ of news://comp.lang.vhdl
• Designers Guide to VHDL
• IEEE VASG (VHDL Analysis and Standardization Group) - Official VHDL Working Group
• A VHDL reference design - UART (Testbench for the design)
• GHDL, a complete Free Software VHDL compiler/simulator, built on top of GCC.
• John's FPGA Page - List of VHDL and FPGA resources, including VHDL tutorials.
• www.opencores.org - A home of many open source VHDL and Verilog projects

The GNU Compiler Collection (usually shortened to GCC) is a set of programming language compilers produced by the GNU Project. ... Open source refers to projects that are open to the public and which draw on other projects that are freely available to the general public. ... Verilog is a hardware description language (HDL) used to model electronic systems. ...

Further reading

• Johan Sandstrom. "Comparing Verilog to VHDL Syntactically and Semantically", Integrated System Design, EE Times, October 1995.  — Sandstrom presents a table relating VHDL constructs to Verilog constructs.
• Qualis Design Corporation (2000-07-20). "VHDL quick reference card". 1.1. Qualis Design Corporation.
• Qualis Design Corporation (2000-07-20). "1164 packages quick reference card". 1.0. Qualis Design Corporation.
• Qualis Design Corporation (2007-03-29). "VHDL quick reference card". 2.2. Qualis Design Corporation.
• Qualis Design Corporation (2007-03-29). "1164 packages quick reference card". 2.2. Qualis Design Corporation.