Verilog is a hardware description language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, verification, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction. In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. ... Electronics is the study of the flow of charge through various materials and devices such as, semiconductors, resistors, inductors, capacitors, nano-structures, and vacuum tubes. ... It has been suggested that this article or section be merged with Analog electronics. ... Digital circuits are electric circuits based on a number of discrete voltage levels. ... A mixed-signal integrated circuits combines analog and digital circuitry. ... In computer science, abstraction is a mechanism and practice to reduce and factor out details so that one can focus on a few concepts at a time. ...

The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. The language is case-sensitive, has a preprocessor like C, and the major control flow keywords, such as "if" and "while", are similar. The formatting mechanism in the printing routines and language operators and their precedence are also similar. C is a general-purpose, procedural, imperative computer programming language developed in 1972 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system. ... Text sometimes exhibits case sensitivity, that is, words can differ in meaning based on the differing use of uppercase and lowercase letters. ... In computer science, a preprocessor is a program that processes its input data to produce output that is used as input to another program. ... In computer science control flow (or alternatively, flow of control) refers to the order in which the individual statements or instructions of an imperative program are performed or executed. ... In computer programming, a keyword is a word or identifier that has a particular meaning to the programming language. ... Programming languages generally have a set of operators that are similar to operators in mathematics: they are somehow special functions. ... This article is about the concept of operator precedence. ...

The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in Verilog require a bit width along with their base, consequently these differ. Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities. Finally, the concept of time —so important to a HDL— won't be found in C. SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. ...

The language differs from a conventional programming language in that the execution of statements is not strictly linear. A Verilog design consists of a hierarchy of modules. Modules are defined with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires and registers. Concurrent and sequential statements define the behaviour of the module by defining the relationships between the ports, wires, and registers. Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But all concurrent statements and all begin/end blocks in the design are executed in parallel. A module can also contain one or more instances of another module to define sub-behavior. A programming language is an artificial language that can be used to control the behavior of a machine, particularly a computer. ... A statement is the minimal unit of structuring in imperative programming languages. ...

A subset of statements in the language is synthesizable. If the modules in a design contain only synthesizable statements, software can be used to transform or synthesize the design into a netlist that describes the basic components and connections to be implemented in hardware. The netlist may then be transformed into, for example, a form describing the standard cells of an integrated circuit (e.g. an ASIC) or a bitstream for a programmable logic device (e.g. a FPGA). Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL) or behavioral) is turned into a design implementation in terms of logic gates. ... The word netlist can be used in several different domains, but perhaps the most popular is in the electronic design domain. ... Standard Cell design involves compiling Hardware definition Language HDL designs into standard logic libraries. ... Integrated circuit showing memory blocks, logic and input/output pads around the periphery Microchips with a transparent window, showing the integrated circuit inside. ... This article does not cite any references or sources. ... A bitstream or bit stream is a time series of bits. ... A programmable logic device or PLD is an electronic component used to build digital circuits. ... A field-programmable gate array or FPGA is a gate array that can be reprogrammed after it is manufactured, rather than having its programming fixed during the manufacturing — a programmable logic device. ...

History

Beginning

Verilog was invented by Phil Moorby at Automated Integrated Design Systems (later renamed to Gateway Design Automation) in 1985 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators. Phil Moorby is a United States engineer and computer scientist. ... Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. ... 1985 (MCMLXXXV) was a common year starting on Tuesday of the Gregorian calendar. ... Cadence Design Systems, Inc (Nasdaq: CDN, NYSE: CDN) is an electronic design automation (EDA) software company, founded in 1988 by the merger of SDA Systems and ECAD. As of 2004, Cadence is the worlds largest supplier of electronic design technologies and engineering services. ... MCMXC redirects here; for the Enigma album, see MCMXC a. ... Logic simulation is the use of a computer program to simulate the operation of a digital circuit. ...

Verilog-95

With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. VHDL, or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. ... Standardization, in the context related to technologies and industries, is the process of establishing a technical standard among competing entities in a market, where this will bring benefits without hurting competition. ... Accellera was founded in 2000 from the merger of Open Verilog International and VHDL International. ... The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ... The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ...

Verilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001. The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ...

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed-operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the boolean-algebra to determine its correct value.) The same function under Verilog-2001 can be more succintly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision-operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system-tasks. And finally, a few syntax additions were introduced to improve code-readability (eg. always @*, named-parameter override, C-style function/task/module header declaration.)

Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages.

Verilog 2005

Verilog 2005, IEEE Standard 1364-2005, focus mostly on minor corrections, as any language improvement was done as a separate project, known as SystemVerilog. The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ... SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. ...

The latest versions of the language include support for analog and mixed signal modelling. These are referred to as Verilog-AMS. Verilog-AMS is a derivative of the hardware description language (HDL) Verilog (IEEE 1364-1995 Verilog HDL). ...

SystemVerilog

Main article: SystemVerilog

Systemverilog is a superset of Verilog-2005, with many new features and capabilities to aide design-verification and design-modeling. SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. ...

The advent of High Level Verification languages such as OpenVera, and Verisity's E language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera were donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog. OpenVera is a Hardware Verification Language developed by Synopsys. ... Synopsys, Inc. ... Accellera was founded in 2000 from the merger of Open Verilog International and VHDL International. ... The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ...

Example

A hello world program looks like this: A hello world program is a software program that prints out Hello world! on a display device. ...

 module main; initial begin $display("Hello world!"); $finish; end endmodule 

A simple example of two flip-flops follows: In digital circuits, the flip-flop, latch, or bistable multivibrator is an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. ...

 module toplevel(clock,reset); input clock; input reset; reg flop1; reg flop2; always @ (posedge reset or posedge clock) if (reset) begin flop1 <= 0; flop2 <= 1; end else begin flop1 <= flop2; flop2 <= flop1; end endmodule 

The "<=" operator in verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" assignment. When the simulation runs, all of the signals assigned with a "<=" operator have their assignment scheduled to occur after all statements occurring during the same point in time have executed. After all the statements have been executed for one event, the scheduled assignments are performed. This makes it easier to code behaviours that happen simultaneously.

In the above example, flop1 is assigned flop2, and flop2 is assigned flop1. These statements are executed during the same time event. Since the assignments are coded with the "<=" non-blocking operator, the assignments are scheduled to occur at the end of the event. Until then, all reads to flop1 and flop2 will use the values they had at the beginning of the time event.

This means that the order of the assignments are irrelevant and will produce the same result. flop1 and flop2 will swap values every clock.

The other choice for assignment is an "=" operator and this is known as a blocking assignment. When the "=" operator is used, things occur in the sequence they occur much like a procedural language.

In the above example, if the statements had used the "=" blocking operator instead, then the order of the statements would affect the behaviour. If the same code were used but changed to "=" operators, the reset would set flop2 to a 1, and flop1 to a 0. A clock event would set flop1 to flop2 (a 1) and this assignment would happen immediately. The next statement would assign flop2 to flop1, which is now a 1. Rather than swap values every clock, flop1 and flop2 would both become 1 and remain that way.

An example counter circuit follows: In general, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. ...

 module Div20x (rst, clk, cet, cep, count,tc); // TITLE 'Divide-by-20 Counter with enables' // enable CEP is a clock enable only // enable CET is a clock enable and // enables the TC output // a counter using the Verilog language parameter size = 5; parameter length = 20; input rst; // These inputs/outputs represent input clk; // connections to the module. input cet; input cep; output [size-1:0] count; output tc; reg [size-1:0] count; // Signals assigned // within an always // (or initial)block // must be of type reg wire tc; // Other signals are of type wire // The always statement below is a parallel // execution statement that // executes any time the signals // rst or clk transition from low to high always @ (posedge clk or posedge rst) if (rst) // This causes reset of the cntr count <= 5'b0; else if (cet && cep) // Enables both true begin if (count == length-1) count <= 5'b0; else count <= count + 5'b1; // 5'b1 is 5 bits end // wide and equal // to the value 1. // the value of tc is continuously assigned // the value of the expression assign tc = (cet && (count == length-1)); endmodule 

An example of delays:

 ... reg a, b, c, d; wire e; ... always @(b or e) begin a = b & e; b = a | b; #5 c = b; d = #6 c ^ e; end 

The always clause above illustrates the other type of method of use, i.e. the always clause executes any time any of the entities in the list change, i.e. the b or e change. When one of these changes, immediately a and b are assigned new values. After a delay of 5 time units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away.

Signals that are driven from within a process (an initial or always block) must be of type reg. Signals that are driven from outside a process must be of type wire. The keyword reg does not necessarily infer a hardware register.

Definition of Constants

The definition of constants in Verilog supports the addition of a width parameter. The basic syntax is:

<Width in bits>'<base letter><number>

Examples:

• 12'h123 - Hexidecimal 123 (using 12 bits)
• 20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
• 4'b1010 - Binary 1010 (using 4 bits)
• 6'o77 - Octal 77 (using 6 bits)

Synthesizeable constructs

As mentioned previously, there are several basic templates that can be used to represent hardware.

 // Mux examples - Three ways to do the same thing. // The first example uses continuous assignment wire out ; assign out = sel ? a : b; // the second example uses a procedure // to accomplish the same thing. reg out; always @(a or b or sel) out = sel ? a: b; // Finally - you can use if/else in a // procedural structure. reg out; always @(a or b or sel) if (sel) out = a; else out = b; 

The next interesting structure is a transparent latch; it will pass the input to the output when the gate signal is set for "pass-through", and captures the input and store it upon transition of the gate signal to "hold". The output will remain stable regardless of the input signal while the gate is set to "hold". In the example below the "pass-through" level of the gate would be when the value of the if clause is true, i.e. gate = 1. This is read "if gate is true, the din is fed to latch_out continuously." Once the if clause is false, the last value at latch_out will remain and is independent of the value of din.

 // Transparent latch example reg out; always @(gate or din) if(gate) out = din; // Pass through state // Note that the else isn't required here. The variable // out will follow the value of din while gate is high. // When gate goes low, out will remain constant. 

The flip-flop is the next significant template; in verilog, the D-flop is the simplest, and it can be modeled as:

 reg q; always @(posedge clk) q <= d; 

The significant thing to notice in the example is the use of the non-blocking assignment. A basic rule of thumb is to use <= when there is a posedge or negedge statement within the always clause.

A variant of the D-flop is one with an asynchronous reset; there is a convention that the reset state will be the first if clause within the statement.

 reg q; always @(posedge clk or posedge reset) if(reset) q <= 0; else q <= d; 

The next variant is including both an asynchronous reset and asynchronous set condition; again the convention comes into play, i.e. the reset term is followed by the set term.

 reg q; always @(posedge clk or posedge reset or posedge set) if(reset) q <= 0; else if(set) q <= 1; else q <= d; 

The final basic variant is one that implements a D-flop with a mux feeding its input. The mux has a d-input and feedback from the flop itself. This allows a gated load function.

 // Basic structure with an EXPLICIT feedback path always @(posedge clk) if(gate) q <= d; else q <= q; // explicit feedback path // The more common structure ASSUMES the feedback is present // This is a safe assumption since this is how the // hardware compiler will interpret it. This structure // looks much like a Latch. The differences are the // '''@(posedge clk)''' and the non-blocking '''<=''' // always @(posedge clk) if(gate) q <= d; // the "else" mux is "implied" 

Looking at the original counter example you can see a combination of the basic asynchronous reset flop and Gated input flop used. The register variable count is set to zero on the rising edge or rst. When rst is 0, the variable count will load new data when cet && cep is true.

Initial and Always

There are two separate ways of declaring a verilog process. These are the always and the initial keywords. The always keyword indicates a free-running process that triggers on the accompanying event-control (@) clause. The initial keyword indicates a process executes exactly once. Both constructs begin execution at simulator time 0, and both execute until the end of the block. Once an always block has reached its end, it is rescheduled (again). It is a common misconception to believe that an initial block will execute before an always block. In fact, it is better to think of the initial-block as a special-case of the always-block, one which terminates after it completes for the first time.

 //Examples: initial begin a = 1; // Assign a value to reg a at time 0 #1; // Wait 1 time unit b = a; // Assign the value of reg a to reg b end always @(a or b) // Anytime a or b CHANGE, run the process begin if (a) c = b; else d = ~b; end // Done with this block, now return to the top (i.e. the @ event-control) always @(posedge a)// Run whenever reg a has a low to high change a <= b; 

These are the classic uses for these two keywords, but there are two significant additional uses. The most common of these is an always keyword without the @() sensitivity list. It is possible to use always as shown below:

 always begin // Always begins executing at time 0 and NEVER stops clk = 0; // Set clk to 0 #1; // Wait for 1 time unit clk = 1; // Set clk to 1 #1; // Wait 1 time unit end // Keeps executing - so continue back at the top of the begin 

The always keyword acts similar to the "C" construct while(1) {..} in the sense that it will execute forever.

The other interesting exception is the use of the initial keyword with the addition of the forever keyword.

The example below is functionally identical to the always example above.

 initial forever // Start at time 0 and repeat the begin/end forever begin clk = 0; // Set clk to 0 #1; // Wait for 1 time unit clk = 1; // Set clk to 1 #1; // Wait 1 time unit end 

Fork/Join

The fork/join pair are used by Verilog to create parallel processes. All statements (or blocks) between a fork/join pair begin execution simultaneously upon execution flow hitting the fork. Execution continues after the join upon completion of the longest running statement or block between the fork and join.

 initial fork $write("A"); // Print Char A $write("B"); // Print Char B begin #1; // Wait 1 time unit $write("C");// Print Char C end join 

The way the above is written, it is possible to have either the sequences "ABC" or "BAC" print out. The order of simulation between the first $write and the second $write depends on the simulator implementation. This illustrates one of the biggest issues with Verilog. You can have race conditions where the language execution order doesn't guarantee the results.

Race Conditions

The order of execution isn't always guaranteed within verilog. This can best be illustrated by a classic example. Consider the code snippet below:

 initial a = 0; initial b = a; initial begin #1; $display("Value a=%b Value of b=%b",a,b); end 

What will be printed out for the values of a and b? Well - it could be 0 and 0, or perhaps 0 and X! This all depends on the order of execution of the initial blocks. If the simulators scheduler works from the top of the file to the bottom, then you would get 0 and 0. If it begins from the bottom of the module and works up, then b will receive the initial value of a at the beginning of the simulation before it has been initialized to 0 (the value of any variable not set explicitily is set to X.) This is the way you can experience a race condition in a simulation. So be careful! Note that the 3rd initial block will execute as you expect because of the #1 there. That is a different point on the time wheel beyond time 0, consequently both of the earlier initial blocks have completed execution.

Operators

System tasks

System tasks are available to handle simple I/O, and various design measurement functions. All system tasks are prefixed with $ to distinguish them from user tasks and functions. This section presents a short list of the most often used tasks. It is by no means a comprehensive list.

• $display - Print to screen a line followed by an automatic newline.
• $write - Print to screen a line without the newline.
• $swrite - Print to variable a line without the newline.
• $sscanf - Read from variable a format-specified string. (*Verilog-2001)
• $fopen - Open a handle to a file (read or write)
• $fdisplay - Write to file a line followed by an automatic newline.
• $fwrite - Write to file a line without the newline.
• $fscanf - Read from file a format-specified string. (*Verilog-2001)
• $fclose - Close and release an open file-handle.
• $readmemh - Read hex file content into a memory array.
• $readmemb - Read binary file content into a memory array.
• $monitor - Print out all the listed variables when any change value.
• $time - Value of current simulation time.
• $dumpfile - Declare the VCD (Value Change Dump) format output file name.
• $dumpvars - Turn on and dump the variables.
• $dumpports - Turn on and dump the variables in Extended-VCD format.
• $random - Return a random value.

VCD - Value Change Dump format - an ASCII file that contains the Changes in Values of Signals. This is a STANDARD format and is compatible between different waveform viewers etc. ...

Program Language Interface (PLI)

Program Language Interface provides a programmer with transferring control from Verilog to a program function written in C language. It also provides task functions named tf_putlongp() and tf_getlongp which are used to write and read the argument of the current Verilog task or function, respectively.

This capability enables Verilog to cooperate with other programs written in C language such as test harness, Instruction Set Simulator of microcontroller, debugger, etc. In software testing, a test harness or automated test framework is a collection of software and test data configured to test a program unit by running it under varying conditions and monitor its behavior and outputs. ... An Instruction Set Simulator (ISS) is a simulation model, usually coded in a high-level language, which mimics the behavior of a processor by reading instructions and maintaining internal variables which represent the processors registers. ... It has been suggested that this article or section be merged with embedded microprocessor. ... A debugger is a computer program that is used to test and debug other programs. ...

Simulation software

Verilog simulation software started as a proprietary product offered by a single company. Today, Verilog simulators are available from the major commercial EDA vendors (Mentor, Synopsys, Cadence.) Modern simulators bundle the core simulator with a complete development environment: editor, waveform viewer, and RTL-level browser. These commercial products are priced and licensed toward corporate users.

For home/personal use, Aldec, LogicSim, Syncad, and Xilinx offer affordable simulators for the x86 Windows 2000/XP platform.

Additionally, several open-source Verilog simulators are under development. Of these, Icarus Verilog has the greatest maturity and largest userbase. Additionally, limited-functionality editions of the Modelsim simulator are downloadable free of charge, from both www.mentor.com and www.xilinx.com. It has been suggested that Open source culture be merged into this article or section. ... Icarus Verilog is an open source implementation of the Verilog hardware description language. ...

See List of Verilog Simulators for additional information. Verilog is a hardware description language (HDL) used to model electronic systems. ...

References

• Johan Sandstrom. "Comparing Verilog to VHDL Syntactically and Semantically", Integrated System Design, EE Times, October 1995.  — Sandstrom presents a table relating Verilog constructs to VHDL constructs.

VHDL, or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. ...

See also

• VHDL
• SystemC
• SystemVerilog
• Property Specification Language

VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. ... SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power during transaction-level modeling and behavioral modeling. ... SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. ... Property Specification Language is a language standardized by Accellera for specifying properties or assertions about hardware designs. ...

External links

Verilog Resources

• verilog-ams – One of the few thorough and genuinely helpful pages that Google seems to miss.

• Asic-World – Extensive free online tutorial with many examples.
• Verilog.net – Premiere List of Verilog Resources on the Internet.
• Digital Computer Courses ("Politehnica" University of Bucharest).
• Verilog Grammar for flex and bison available as open source.
• Qualis Design Corporation (2000-07-20). "Verilog HDL quick reference card". 1.1. Qualis Design Corporation.
• A Verilog Designers Guide
• Lots of Verilog Examples
• Sutherland-hdl reference Guide

flex (fast lexical analyzer generator) is a free software alternative to Lex. ... GNU bison is a free parser generator computer program written for the GNU project, and available for virtually all common operating systems. ... 2000 (MM) was a leap year starting on Saturday of the Gregorian calendar. ... July 20 is the 201st day (202nd in leap years) of the year in the Gregorian calendar, with 164 days remaining. ...

Standards Development

• IEEE Std 1364-2001 – The official standard for Verilog 2001 (not free).
• IEEE P1364 – Working group for Verilog (inactive).
• IEEE P1800 – Working group for SystemVerilog (replaces above).
• Verilog syntax – A description of the syntax in Backus-Naur form. This predates the IEEE-1364 standard.
• Verilog 2001 syntax – A heavily linked BNF syntax for Verilog 2001 (generated by EBNF tools).

The Backus-Naur form (BNF) (also known as Backus normal form) is a metasyntax used to express context-free grammars: that is, a formal way to describe formal languages. ...

Software Links

• Active HDL - A mixed-languages simulator, supporting Verilog-2001 and SystemVerilog.
• GPL Cver - An open-source Verilog simulator, supporting Verilog-2001 and the complete Verilog Procedural Interface.
• Icarus Verilog - An open-source Verilog simulator and synthesis tool, supporting Verilog-2001 and (partially) Verilog Procedural Interface.
• LogicSim - A low-cost Windows-only Verilog simulator.
• ModelSim - A mixed-languages simulator, supporting Verilog-2001 and SystemVerilog.
• VCS - A fast Verilog simulator, mainly UNIX-based.
• VeriLogger Extreme - Verilog 2001 simulator for Windows and Unix