In circuit design

In circuit design, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases timing becomes more critical and there is less variation that can be tolerated while still functioning properly. A synchronous circuit is a circuit in which the parts are synchronized by means of a clock subcircuit. ... In synchronous digital electronics, such as most computers, a clock signal is a signal used to coordinate the actions of two or more circuits. ... In electronics, capacitive coupling is the transfer of energy from one circuit to another by means of the mutual capacitance between the circuits. ...

Harmful skew

There are two types of clock skew negative skew and positive skew. Positive skew is when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew is the opposite, when the receiving register gets the clock earlier than the sending register.

There are two types of violations that can be caused by clock skew. One problem is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or might destroy the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew can cause both violations, but negative skew can never cause a hold violation.

Beneficial skew

Clock skew can also benefit a circuit by decreasing the clock period at which the circuit will operate correctly. For each source register and destination register connected by a path, the following inequalities must hold:

1. 
2. 
3. a. or
   b.

where

• T is the clock period,
• reg is the source register's clock to Q delay,
• path_max is the path with the longest delay from source to destination,
• S is the setup time of the destination register
• path_min is the path with the shortest delay from source to destination,
• H is the hold time of the destination register,
• (s_d − s_s) represents the clock skew from the source to the destination registers,
• s_d is the clock skew to the destination register, and
• s_s is the clock skew to the source register.

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. ... The introduction of this article does not provide enough context for readers unfamiliar with the subject. ...

On a network

On a network such as the internet, clock skew describes the difference in time shown by the clocks at the different nodes on the network. It is usually an unavoidable phenomenon (at least if one looks at milli-second resolutions), but clock skew of tens of minutes or more is also quite common. A number of protocols (e.g. Network Time Protocol) have been designed to reduce clock skew, and produce more stable functions. The Network Time Protocol (NTP) is a protocol for synchronizing the clocks of computer systems over packet-switched, variable-latency data networks. ...

See also

• Clock drift

Clock drift refers to several related phenomena where a clock does not run in the exact right speed compared to another clock. ...

References

• Friedman, E.G., ed., Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, 1995.
• Maheshwari, N., and Sapatnekar, S.S., Timing Analysis and Optimization of Sequential Circuits, Kluwer, 1999.
• Tam, S., Limaye, D.L., and Desai, U.N., "Clock Generation and Distribution for the 130-nm Itanium 2 Processor with 6-MB On-Die L3 Cache", in IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, April 2004.

In addition, there are hundreds of articles on various technical details of this subject (Clock skew). These are normally presented at conferences such as the Design Automation Conference (DAC) and the International Conference on Computer-Aided Design (ICCAD), along with many smaller conferences. The main journal in the field is IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems (Web page here). Most of these journals and conference proceedings are published by the IEEE or the ACM. You can search the IEEE on-line library and the ACM digital library and view the abstracts for free. Downloading full text requires purchase, society membership, or a site license; many schools and companies have such licenses already. The Design Automation Conference, or DAC is a combination of a technical conference and a trade show, both specializing in electronic design automation. ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, often abbreviated IEEE TCAD or IEEE Transactions on CAD, is a technical journal devoted to the design, analysis, and use of computer programs that aid in the design of integrated circuits and systems. ... The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-e) is an international non-profit, professional organization for the advancement of technology related to electricity. ... The Association for Computing Machinery, or ACM, was founded in 1947 as the worlds first scientific and educational computing society. ...